74HCT163DB,112 NXP

74HC163 74HCT163 Presettable synchronous 4-bit binary counter synchronous reset Rev. 3 2 June 2014 Product data sheet 1. General description The 74HC163 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula: 1 f = ---------------------------------------------------------------------------------------- max t CPtoTC +tCEPtoCP Pmax SU 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC163: CMOS level For 74HCT163: TTL level Synchronous counting and loading 2 count enable inputs for n-bit cascading Synchronous reset Positive-edge triggered clock ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C74HC163 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter synchronous reset 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74HC163N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HCT163N 74HC163D 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT163D 74HC163DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HCT163DB 74HC163PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT163PW 4. Functional diagram 3( (/ /5/ 05 < /2 &,5&8,75 &(3 &(7 &(7 7& &(3 7& 05 ,1+ %,1 5< 4 &3 &2817(5 4 DDD DDD Fig 1. Functional diagram Fig 2. Logic symbol & 7 DDD Fig 3. IEC logic symbol 74HC HCT163 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 2 June 2014 2 of 24 & * * 0 5 5 &7 4 4 4 &3 4 4 4 &3 3( 3