74HCT175PW,112 NXP

74HC175 74HCT175 Quad D-type flip-flop with reset positive-edge trigger Rev. 6 4 February 2021 Product data sheet 1. General description The 74HC175 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Input levels: For 74HC175: CMOS level For 74HCT175: TTL level Four edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC175D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT175D 74HC175PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT175PWNexperia 74HC175 74HCT175 Quad D-type flip-flop with reset positive-edge trigger 4. Functional diagram 9 C1 1 R 9 2 2 CP Q0 4 4 1D D0 3 3 Q0 7 7 Q1 5 5 D1 6 6 Q1 10 Q2 12 10 D2 11 12 Q2 11 15 Q3 13 D3 15 14 Q3 13 MR 14 1 aaa-008921 aaa-008922 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 D1 D2 D3 D Q D Q D Q D Q FF1 FF2 FF3 FF4 CP CP CP CP Q Q Q Q RD RD RD RD CP MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 aaa-008927 Fig. 3. Logic diagram 74HC HCT175 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 4 February 2021 2 / 16