74HCT2G00GD NXP

74HC2G00 74HCT2G00 Dual 2-input NAND gate Rev. 5 26 September 2013 Product data sheet 1. General description The 74HC2G00 74HCT2G00 is a dual 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC2G00: CMOS level For 74HCT2G00: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G00DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74HCT2G00DP 74HC2G00DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74HCT2G00DC 74HC2G00GD 40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74HCT2G00GDNXP Semiconductors 74HC2G00 74HCT2G00 Dual 2-input NAND gate 4. Marking Table 2. Marking code 1 Type number Marking code 74HC2G00DP H00 74HCT2G00DP T00 74HC2G00DC H00 74HCT2G00DC T00 74HC2G00GD H00 74HCT2G00GD T00 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 & 7 2 1 1A 1Y 7 2 1B B 5 2A 5 2Y 3 & 3 Y 6 2B 6 A mna712 mna099 mna713 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one driver) 6. Pinning information 6.1 Pinning 74HC2G00 74HCT2G00 1A 1 8 V CC 74HC2G00 1B 2 7 1Y 74HCT2G00 2Y 3 6 2B 1A 1 8 V CC 1B 2 7 1Y GND 4 5 2A 2Y 3 6 2B GND 4 5 2A 001aai256 Transparent top view 001aai255 Fig 4. Pin configuration SOT505-2 (TSSOP8) and Fig 5. Pin configuration SOT996-2 (XSON8) SOT765-1 (VSSOP8) 74HC HCT2G00 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 26 September 2013 2 of 14