74HC4051 74HCT4051 8-channel analog multiplexer/demultiplexer Rev. 7 19 July 2012 Product data sheet 1. General description The 74HC4051 74HCT4051 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC4051 74HCT4051 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0 to S2. V and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). CC The V to GND ranges are 2.0 V to 10.0 V for 74HC4051 and 4.5 V to 5.5 V for CC 74HCT4051. The analog inputs/outputs (Y0 to Y7, and Z) can swing between V as a CC positive limit and V as a negative limit. V V may not exceed 10.0 V. EE CC EE For operation as a digital multiplexer/demultiplexer, V is connected to GND (typically EE ground). 2. Features and benefits Wide analog input voltage range from 5 V to +5 V Low ON resistance: 80 (typical) at V V =4.5 V CC EE 70 (typical) at V V =6.0 V CC EE 60 (typical) at V V =9.0 V CC EE Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical break before make built-in ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from 40 Cto +85 C and 40 Cto +125 C 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating74HC4051 74HCT4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4051N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HCT4051N 74HC4051D 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT4051D 74HC4051DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HCT4051DB 74HC4051PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT4051PW 74HC4051BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package no leads 16 terminals 74HCT4051BQ body 2.5 3.5 0.85 mm 5. Functional diagram V CC 16 13 Y0 S0 11 14 Y1 15 Y2 S1 10 12 Y3 LOGIC 1-OF-8 1Y4 LEVEL DECODER CONVERSION S2 9 5Y5 2Y6 E 6 4Y7 3Z 87 GND V 001aad543 EE Fig 1. Functional diagram 74HC HCT4051 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 19 July 2012 2 of 31