74LV153PW,112 NXP

74LV153 Dual 4-input multiplexer Rev. 5 12 December 2011 Product data sheet 1. General description The 74LV153 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC153 and 74HCT153. The 74LV153 provides a dual 4-input multiplexer which selects 2 bits of data from up to four sources selected by common data select inputs (S0, S1). The two 4-input multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH. The 74LV153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch, is determined by the logic levels applied to S0 and S1. The logic equations for the outputs are: 1Y = 1E (1I0 S1 S0 + 1I1 S1 S0 + 1I2 S1 S0 + 1I3 S1 S0) 2Y = 2E (2I0 S1 S0 + 2I1 S1 S0 + 2I2 S1 S0 + 2I3 S1 S0) The 74LV153 can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic. 2. Features and benefits Wide operating voltage: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T = 25 C amb Non-inverting outputs Separate enable input for each output Common select inputs Permits multiplexing from n lines to 1 line Enable line provided for cascading (n lines to 1 line) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C74LV153 NXP Semiconductors Dual 4-input multiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV153N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74LV153D 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV153DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74LV153PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 4. Functional diagram 1 2E 1I0 6 1I1 5 1Y 7 MUX 1I2 4 1I3 3 S0 14 6 5 4 3 10 11 12 13 S1 2 1I0 1I1 1I2 1I3 2I0 2I1 2I2 2I3 2I0 14 S0 10 2I1 2 S1 11 2Y 9 MUX 2I2 1 1E 12 2I3 15 2E 13 1Y 2Y 2E 7 9 001aal843 15 001aal844 Fig 1. Logic symbol Fig 2. Functional diagram 74LV153 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 12 December 2011 2 of 17