74LV4020N,112 NXP

74LV4020 14-stage binary ripple counter Rev. 01 29 November 2005 Product data sheet 1. General description The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HCT4020. The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle ip-op. 2. Features Optimized for low-voltage applications: 1.0 V to 5.5 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical LOW-level output voltage (peak) or output ground bounce: V < 0.8 V at OL(p) V = 3.3 V and T =25 C CC amb Typical HIGH-level output voltage (valley) or output V undershoot: V >2V at OH OH(v) V = 3.3 V and T =25 C CC amb ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Multiple package options Specied from - 40 C to +80 C and from - 40 C to +125 C. 3. Applications Frequency dividing circuits Time delay circuits Control counters74LV4020 Philips Semiconductors 14-stage binary ripple counter 4. Quick reference data Table 1: Quick reference data GND = 0 V; T =25 C; t =t = 2.5 ns. amb r f Symbol Parameter Conditions Min Typ Max Unit t , propagation delay C = 15 pF; V = 3.3 V PHL L CC t PLH CP to Q0 - 12 - ns Qn to Q(n+1) - 7 - ns t propagation delay C = 15 pF; V = 3.3 V PHL L CC MR to Qn - 16 - ns f maximum input clock C = 15 pF; V = 3.3 V - 100 - MHz max L CC frequency C input capacitance - 3.5 - pF i [1] C power dissipation per gate; V = GND to -20 - pF PD I capacitance V CC [1] C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz; i f = output frequency in MHz; o C = output load capacitance in pF; L V = supply voltage in V; CC N = number of inputs switching; 2 (C V f ) = sum of outputs. L CC o 5. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74LV4020N - 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74LV4020D - 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74LV4020DB - 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74LV4020PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74LV4020_1 Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 29 November 2005 2 of 20