74LVC1G00GM NXP

74LVC1G00 Single 2-input NAND gate Rev. 10 2 July 2012 Product data sheet 1. General description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Cto+85 C and 40 C to +125 C74LVC1G00 NXP Semiconductors Single 2-input NAND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G00GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; SOT353-1 5 leads; body width 1.25 mm 74LVC1G00GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G00GM 40 C to +125 C XSON6 plastic extremely thin small outline package; SOT886 no leads; 6 terminals; body 1 1.45 0.5 mm 74LVC1G00GF 40 C to +125 C XSON6 plastic extremely thin small outline package; SOT891 no leads; 6 terminals; body 1 1 0.5 mm 74LVC1G00GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 1.0 0.35 mm 74LVC1G00GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 1.0 0.35 mm 74LVC1G00GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely SOT1226 thin small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm 4. Marking Table 2. Marking codes [1] Type number Marking 74LVC1G00GW VA 74LVC1G00GV V00 74LVC1G00GM VA 74LVC1G00GF VA 74LVC1G00GN VA 74LVC1G00GS VA 74LVC1G00GX VA [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 1 B & Y 4 4 Y 2 A 2 A mna097 mna098 mna099 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74LVC1G00 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 10 2 July 2012 2 of 19