74LVC823APW,118 NXP

74LVC823A 9-bit D-type flip-flop with 5 V tolerant inputs/outputs positive edge-trigger 3-state Rev. 4 8 April 2013 Product data sheet 1. General description The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Flow-through pinout architecture 9-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C.74LVC823A NXP Semiconductors 9-bit D-type flip-flop 5 V tolerance positive edge-trigger 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC823AD 40 C to +125 C SO24 plastic small outline package 24 leads SOT137-1 body width 7.5 mm 74LVC823ADB 40 C to +125 C SSOP24 plastic shrink small outline package 24 leads SOT340-1 body width 5.3 mm 74LVC823APW 40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74LVC823ABQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1 thin quad flat package no leads 24 terminals body 3.5 5.5 0.85 mm 4. Functional diagram 2 D0 Q0 23 3 D1 Q1 22 4 D2 Q2 21 5 D3 Q3 20 FF0 6 D4 Q4 19 3-STATE to OUTPUTS FF8 7 D5 Q5 18 8 D6 Q6 17 9 D7 Q7 16 10 D8 Q8 15 13 CP 11 MR 14 CE 1 OE 001aaa849 Fig 1. Functional diagram 74LVC823A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 8 April 2013 2 of 21