74LVCU04ABQ NXP

74LVCU04A Hex inverter Rev. 6 9 August 2011 Product data sheet 1. General description The 74LVCU04A is a general purpose hex inverter. Each of the six inverters is a single stage with unbuffered outputs. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVCU04AD 40 Cto +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LVCU04ADB 40 Cto +125 C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LVCU04APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LVCU04ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm74LVCU04A NXP Semiconductors Hex inverter 4. Functional diagram 1 1 2 1 1A 1Y 2 1 3 4 3 2A 2Y 4 1 5 6 5 3A 3Y 6 1 9 8 4Y 9 4A 8 V V CC CC 1 5A 5Y 10 11 11 10 100 nA nY 13 6A 6Y 12 1 13 12 mna926 mna927 mna925 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Schematic diagram for one inverter 5. Pinning information 5.1 Pinning terminal 1 1A 1 14 V index area CC 1Y 2 13 6A 1Y 2 13 6A 3 12 2A 6Y 2A 3 12 6Y 2Y 4 04 11 5A 4 11 2Y 04 5A 3A 5 (1) 10 5Y GND 3A 5 10 5Y 3Y 6 9 4A 3Y 6 9 4A 001aad063 GND 7 8 4Y Transparent top view 001aad062 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14 74LVCU04A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 9 August 2011 2 of 17 GND 7 1 1A 4Y 8 14 V CC