74LVT00D,112 NXP

INTEGRATED CIRCUITS 74LVT00 3.3V Quad 2-input NAND gate Product specification 1996 Aug 15 IC24 Data Handbook Philips Semiconductors Product specification 3.3V Quad 2-input NAND gate 74LVT00 QUICK REFERENCE DATA CONDITIONS SYMBOL PARAMETER T = 25C TYPICAL UNIT amb GND = 0V Propagation delay t C = 50pF 2.7 PLH L An or Bn ns t V = 3.3V 2.7 PHL CC to Yn C Input capacitance V = 0V or 3.0V 3 pF IN I I Total supply current Outputs Low V = 3.6V 1 mA CCL CC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO 40C to +85C 74LVT00 D 74LVT00 D SOT108-1 14-Pin Plastic SSOP 40C to +85C 74LVT00 DB 74LVT00 DB SOT337-1 14-Pin Plastic TSSOP 40C to +85C 74LVT00 PW 74LVT00PW DH SOT402-1 LOGIC SYMBOL PIN CONFIGURATION 12 4 5 9 101213 A0 1 14 V CC B0 2 13 B3 Y0 3 12 A3 A0 B0 A1 B1 A2 B2 A3 B3 A1 4 11 Y3 B1 5 10 B2 Y0Y1Y2Y3 Y1 6 9 A2 GND 7 8 Y2 V = Pin 14 CC SA00333 36 8 11 GND = Pin 7 SA00334 PIN DESCRIPTION LOGIC SYMBOL (IEEE/IEC) PIN SYMBOL NAME AND FUNCTION NUMBER & 1 3 1, 2, 4, 5, 9, An-Bn Data inputs 2 10, 12, 13 3, 6, 8, 11 Yn Data outputs 4 6 7 GND Ground (0V) 5 14 V Positive supply voltage CC 9 8 10 12 11 13 SF00004 2 1996 Aug 15 853-1858 17183