74VHCT08BQ NXP

74VHC08; 74VHCT08 Quad 2-input AND gate Rev. 01 30 June 2009 Product data sheet 1. General description The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard JESD7-A. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. 2. Features n Balanced propagation delays n All inputs have a Schmitt-trigger action n Inputs accepts voltages higher than V CC n Input levels: u The 74VHC08 operates with CMOS logic levels u The 74VHCT08 operates with TTL logic levels n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC08D - 40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74VHCT08D 74VHC08PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74VHCT08PW 74VHC08BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package; no leads; 14 terminals; 74VHCT08BQ body 2.5 3 0.85 mm74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 2 1 1A 1Y 3 2 1B 4 & 6 4 2A 5 2Y 6 A 5 2B Y 9 3A 3Y 8 9 & 10 3B 8 B 10 mna221 12 4A 4Y 11 13 4B 12 & 11 mna222 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74VHC08 74VHC08 74VHCT08 74VHCT08 terminal 1 1A 1 14 V CC index area 1B 2 13 4B 1B 2 13 4B 1Y 3 12 4A 1Y 3 12 4A 4 11 2A 4Y 4 11 2A 4Y 2B 5 (1) 10 3B GND 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A 001aak041 GND 7 8 3Y Transparent top view 001aak040 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration SO14 and TSSOP14 Fig 5. Pin conguration DHVQFN14 74VHC_VHCT08_1 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 30 June 2009 2 of 14 GND 7 1 1A V 3Y 8 14 CC