Freescale Semiconductor
Document Number: BSC9132
Data Sheet: Technical Data Rev. 0, 03/2014
BSC9132
BSC9132 QorIQ Qonverge
Multicore Baseband
FC-PBGA780
23 mm x 23 mm
Processor
The following list provides an overview of the feature set: TCP/IP acceleration, quality of service, and
classification capabilities
Two high-performance 32-bit e500 cores built on Power
IEEE Std 1588 support
Architecture technology:
Supports SGMII interfaces
36-bit physical addressing
High-speed interfaces supporting the following
Double-precision floating-point support
multiplexing options:
32-Kbyte L1 instruction cache and 32-Kbyte L1 data
One PCI Express interface with 5G support
cache
Four lanes of high-speed serial interfaces (SerDes) to be
Enhanced hardware and software debug support
shared between PCI Express, SGMII, and CPRI
800 Mhz/1 GHz/1.2 GHz clock frequency
High-speed USB controller (USB 2.0)
512-Kbyte L2 cache with ECC; also configurable as
Host and device support
SRAM and stashing memory
Enhanced host controller interface (EHCI)
Two SC3850 core subsystems; each core connects to the
ULPI interface
following:
Enhanced secure digital (SD/MMC) host controller
32 Kbyte 8-way level 1 data/instruction cache
(eSDHC)
(L1 Dcache/ICache)
Integrated Flash controller (IFC), supporting NAND,
512 Kbyte 8-way level 2 unified instruction/data cache
NOR, and general ASIC
(L2 cache/M2 memory)
Two TDM interfaces
Memory management unit (MMU)
Antenna interface controller (AIC), supporting four
Enhanced programmable interrupt controller (EPIC)
industry standard JESD/four custom parallel RF interfaces
Debug and profiling unit (DPU)
(three dual and one single port) and a 2-lane CPRI interface
Two 32-bit quad timers
Universal Subscriber Identity Module (USIM) interface
32 Kbytes of shared M3 memory
Facilitates communication to SIM cards or Eurochip
Multi Accelerator Platform Engine for Pico Base Station
pre-paid phone cards
Baseband Processing (MAPLE-B2P)
Two enhanced serial peripheral interfaces (eSPI)
Supports variable sizes in Fourier Transforms,
Programmable interrupt controller (PIC) compliant with
Convolution, Filtering, Turbo, Viterbi, Chiprate, MIMO
OpenPIC standard
Consists of accelerators for UMTS chip rate processing,
Two DMA controllers
LTE UP/DL channel processing, Matrix Inversion
4-channel DMA on Power Architecture side
operations, and CRC algorithms
32 unidirectional channels, providing up to 16
Two DDR3/DDR3L SDRAM memory controllers support
memory-to-memory channels on DSP side
32-bit with ECC
2
Two I C interfaces
Integrated security engine (ULE CAAM)
Two dual UART (DUART) interfaces
Protocol support includes DES, AES, RNG, CRC, MDE,
96 general-purpose I/O signals
PKE, SHA, and MD5
Eight 32-bit timers
Secure boot capability
Operating temperature (Ta - T ) range: 0105 C
Two enhanced three-speed Ethernet controllers (eTSECs)
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2014 Freescale Semiconductor, Inc. All rights reserved.Table of Contents
1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.22 Universal Subscriber Identity Module (USIM) . . . . . . 106
1.1 Ball Layout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.23 Timers and Timers_32b AC Timing Specifications . . 110
1.2 Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 111
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.1 Power Architecture System Clocking. . . . . . . . . . . . . 111
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .36 3.2 DSP System Clocking . . . . . . . . . . . . . . . . . . . . . . . . 114
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.3 Supply Power Default Setting . . . . . . . . . . . . . . . . . . 115
2.3 Power-Down Requirements . . . . . . . . . . . . . . . . . . . . .42 3.4 PLL Power Supply Design . . . . . . . . . . . . . . . . . . . . . 116
2.4 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.5 Decoupling Recommendations . . . . . . . . . . . . . . . . . 117
2.5 Power-on Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.6 SerDes Block Power Supply Decoupling
2.6 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .43 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 118
2.7 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7 Guidelines for High-Speed Interface Termination . . . 119
2.8 DDR3 and DDR3L SDRAM Controller . . . . . . . . . . . . .48 3.8 Pull-Up and Pull-Down Resistor Requirements. . . . . 119
2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.9 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 120
2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.10 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 120
2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .59 3.11 JTAG Configuration Signals. . . . . . . . . . . . . . . . . . . . 121
2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.12 Guidelines for High-Speed Interface Termination . . . 123
2.13 Integrated Flash Controller (IFC) . . . . . . . . . . . . . . . . .66 3.13 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.14 Enhanced Secure Digital Host Controller (eSDHC) . . .70 3.14 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . 124
2.15 Programmable Interrupt Controller (PIC) Specifications72 4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2.16 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 124
2
2.17 I C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 125
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.19 TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.1 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.20 High-Speed Serial Interface (HSSI) DC Electrical 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.21 Radio Frequency (RF) Interface . . . . . . . . . . . . . . . . .103
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0
2 Freescale Semiconductor