Document Number: DSP56367 Freescale Semiconductor Rev. 2.1, 1/2007 Data Sheet: Technical Data DSP56367 24-Bit Audio Digital Signal Processor Contents 1Overview 1 Overview 1-1 This document briefly describes the DSP56367 24-bit 2 Signal/Connection Descriptions . 2-1 digital signal processor (DSP). The DSP56367 is a 3 Specifications . 3-1 4 Packaging 4-1 member of the DSP56300 family of programmable 5 Design Considerations 5-1 CMOS DSPs. The DSP56367 is targeted to applications A Power Consumption Benchmark A-1 that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. The DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.5 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved.Overview Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage* PIN True Asserted V / V IL OL PIN False Deasserted V / V IH OH PIN True Asserted V / V IH OH PIN False Deasserted V / V IL OL Note:*Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH 8 4 2 16 5 1 6 MEMORY EXPANSION AREA PROGRAM X Y DAX RAM HOST TRIPLE (SPDIF Tx.) ESAI SHI /INSTR. CACHE MEMORY MEMORY INTERFACE INTER- 3K x 24 TIMER INTER- INTER- RAM RAM PROGRAM FACE FACE FACE 13K X 24 7K X 24 ROM ROM ROM 40K x 24 ESAI 1 Bootstrap ROM 32K x 24 8K x 24 192 x 24 PERIPHERAL EXPANSION AREA ADDRESS YAB EXTERNAL GENERATION 18 XAB ADDRESS UNIT PAB BUS ADDRESS SIX CHANNELS DAB SWITCH DMA UNIT 24-BIT DRAM & DSP56300 SRAM BUS 10 INTERFACE Core & CONTROL I - CACHE DDB YDB EXTERNAL 24 INTERNAL DATA BUS XDB DATA SWITCH PDB BUS DATA SWITCH GDB POWER MNGMNT PLL DATA ALU PROGRAM PROGRAM PROGRAM + -> 24X24 56 56-BIT MAC 4 INTERRUPT DECODE ADDRESS JTAG CLOCK TWO 56-BIT ACCUMULATORS CONTROLLER CONTROLLE GENERATOR BARREL SHIFTER GENERATOR OnCE EXTAL 24 BITS BUS MODA/IRQA MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1-1 DSP56367 Block Diagram DSP56367 Technical Data, Rev. 2.1 1-2 Freescale Semiconductor PIO EB PM EB XM EB YM EB