HEF4011B Quad 2-input NAND gate Rev. 5 21 November 2011 Product data sheet 1. General description The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B Inputs and outputs are protected against electrostatic effects 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number Package Name Description Version HEF4011BP DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 HEF4011BT SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 4. Functional diagram 1A 1 3 1Y 1B 2 2A 5 4 2Y 2B 6 3A 8 10 3Y 3B 9 4A 12 11 4Y nA 4B 13 nY nB 001aan874 001aan875 Fig 1. Functional diagram Fig 2. Logic diagram (one gate)HEF4011B NXP Semiconductors Quad 2-input NAND gate 5. Pinning information 5.1 Pinning 1A 1 14 V DD 1B 2 13 4B 1Y 3 12 4A 2Y 4 HEF4011B 11 4Y 5 10 2A 3Y 2B 6 9 3B V 7 8 3A SS 001aan876 Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description nA 1, 5, 8, 12 input nB 2, 6, 9, 13 input nY 3, 4, 10, 11 output V 7 ground (0 V) SS V 14 supply voltage DD 6. Functional description 1 Table 3. Function table Input Output nA nB nY LL H LH H HL H HH L 1 H = HIGH voltage level L = LOW voltage level. HEF4011B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 21 November 2011 2 of 12