IP4774CZ14,118 NXP

IP4774CZ14 VGA interface with integrated h-sync buffer, ESD protection and termination resistor Rev. 01 24 February 2009 Objective data sheet 1. General description The IP4774CZ14 is a VGA or DVI-I interface intended for connection between a video transmitter such as a PC graphics card and a VGA or DVI-I receiver, such as a PC monitor. The IP4774CZ14 has ESD protection for the DDC lines, ESD protection plus buffering for the h-sync line, and high-level ESD protection diodes for the RGB video signal lines. The h-sync signal is buffered by a non-inverting buffer which can accept TTL-level input. The buffer convert TTL-level input to CMOS-level output which swings between V CC(SYNC) and GND. An external termination resistor can be added to achieve the desired termination, which is typically required for the h-sync line of the video interface. The IP4774CZ14 has a typical output resistance (R ) of 10 . O 2. Features n Integrated high-level ESD protection, buffering, sync-signal impedance matching n All pin connections have integrated rail-to-rail clamping diodes providing downstream ESD protection of 8 kV according to IEC 61000-4-2, level 4 n Driver for h-sync line n Line capacitance < 4 pF per channel 3. Applications Buffer and terminating channels, reduce EMI/RFI and provide downstream ESD protection for: n VGA interfaces including DDC channels n Desktop and notebook PCs, LCD TVs and PC monitors n Graphics cards n Set-top boxes n Game consoles n DVD playersIP4774CZ14 NXP Semiconductors VGA port protection with sync buffer 4. Ordering information Table 1. Ordering information Type number Package Name Description Version IP4774CZ14 SSOP14 plastic shrink small outline package 14 leads body width 5.3 mm SOT337-1 5. Functional diagram V V CC(VIDEO) CC(SYNC) 14 9 IP4774CZ14 1 VIDEO 1 2 VIDEO 2 3 VIDEO 3 10 GND 8 BYP 11 n.c. 6 DDC IN1 7 12 DDC IN2 H SYNC OUT 4 H SYNC IN 5 V SYNC IN 13 GND 001aai178 The ESD structure of the IP4774CZ14 enables a receiver and a transmitter application. Fig 1. Functional diagram IP4774CZ14 1 NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 24 February 2009 2 of 12