KIT912H634EVME NXP

Freescale Semiconductor Document Number: MM912 634D1 Rev. 13.0, 6/2015 Technical Data Integrated S12 Based Relay 912 634 Driver with LIN The MM912G634 (48 kB) and MM912H634 (64 kB) are integrated, single package solutions which integrate an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) AE SUFFIX (PB-FREE) AP SUFFIX (PB-FREE) controlled analog die combines system base chip and application 98ASA00173D 98ASH00962A specific functions, including a LIN transceiver. 48 PIN LQFP 48 PIN LQFP-EP Features (7.0 X7.0 mm) (7.0 X7.0 mm) 16-Bit S12 CPU, 64/48 kByte P-FLASH 6.0 kByte RAM 4/2 kByte D-FLASH Background debug (BDM) & debug module (DBG) Die to Die bus interface for transparent memory mapping On-chip oscillator & two independent watchdogs LIN 2.1 Physical layer interface with integrated SCI 10 digital MCU GPIOs shared with SPI (PA70, PE10) 10-Bit, 15 Channel - Analog to Digital converter (ADC) 16-Bit, 4 Channel - Timer module (TIM16B4C) 8-Bit, 2 Channel - Pulse width modulation module (PWM) Six high-voltage / Wake-up inputs (L50) Three low voltage GPIOs (PB20) Low power modes with cyclic sense & forced wake-up Current sense module with selectable gain Reverse battery protected voltage sense module Two protected low-side outputs to drive inductive loads Two protected high-side outputs Chip temperature sensor Hall sensor supply & integrated voltage regulator(s) Battery Sense VSENSE LS1 VS1 MM912 634 Power Supply VS2 Low-side Drivers PGND M LIN Interface LIN LGND LS2 ADC25 ADC Supply AGND ISENSEH* VDD Current Sense Mode 2.5 V Supply ISENSEL* VDDD2D HSUP VDDX 5.0 V Supply Hall Sensor Supply Hall Sensor Hall Sensor VDDRX DGND 5.0 V GPI/O with optional Digital Ground VSSD2D PTB0/AD0/RX/TIM0CH0 pull-up (shared with ADC, VSSRX PTB1/AD1/TX/TIM0CH1 PWM, Timer, and SCI) RESET Reset PTB2/AD2/PWM/TIM0CH2 RESET A HS1 12 V Light/LED and PA0/MISO Switch Supply PA1/MOSI HS2* PA2/SCK PA3/SS 5.0 V Digital I/O PA4 Analog/Digital inputs L0 PA5 L1 PA6 (High Voltage and Wake-up L2 PA7 capable) L3 BKGD/MODC L4* Debug and External PE0/EXTAL L5* Oscillator PE1/XTAL TCLK Analog Test MCU Test TEST TEST A * Feature not availablre in all Analog Options Figure 1. Simplified Application Diagram Freescale Semiconductor, Inc., 2010 - 2015. All rights reserved.1 Ordering Information Table 1. Ordering Information Device Max. Bus Temperature Data Flash Analog (Add an R2 suffix for Tape and Package Frequency in MHz Flash (kB) RAM (kB) (1) Range (T ) (kB) Option A Reel orders) (f ) BUSMAX MM912G634DM1AE -40C to 125C LQFP48-EP 20 A1 (2) (3) (4) MM912G634DV1AE 48 2 2 -40C to 105C MM912G634DV2AP LQFP48 16 A2 MM912H634DM1AE -40C to 125C LQFP48-EP 20 64 4 6 A1 MM912H634DV1AE -40C to 105C Note: 1. See Table 2. 2. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested FLASHSIZE reduced to 48 kB. This limits the usable Flash area to the first 48 kB (0x3 4000-0x3 FFFF). 3. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested Data - FLASHSIZE reduced to 2.0 kB. This limits the usable Data Flash area to the first 2.0 kB (0x0 4400-0x0 4BFF). 4. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested RAMSIZE reduced to 2.0 kB. This limits the usable RAM area to the first 2.0 kB (0x0 2800-0x0 2FFF). (5) Table 2. Analog Options Feature A1 A2 Battery Sense Module YES YES Current Sense Module YES NO 2nd High-side Output (HS2) YES YES Wake-up Inputs (Lx) L0L5 L0L3 Hall Supply Output (HSUP) YES YES LIN Module YES YES Note: 5. This table only highlights the analog die differences between the derivatives. Features highlighted as NO or the Lx Inputs not mentioned are not available in the specific option and not bonded out and/or not tested. See Analog Die Options for detailed information. MM912 634 Analog Integrated Circuit Device Data 2 Freescale Semiconductor