LS1020ASE7KQB NXP

Document Number LS1020A NXP Semiconductors Rev. 3, 05/2016 Data Sheet: Technical Data LS1020A QorIQ LS1020A Data Sheet Features Additional peripheral interfaces One high-speed USB 3.0 controller with integrated ARM Cortex-A7 MPCore compliant with ARMv7- PHY A architecture One high-speed USB 2.0 controller with ULPI LS1020A contains a dual-core Cortex-A7. Each core Enhanced secure digital host controller includes: (eSDHC/MMC/eMMC) 32 KB L1 Instruction Cache (ECC protection) Three I2C controllers 32 KB L1 Data Cache (ECC protection) FlexTimer/PWM NEON Co-processor SPI interface Floating Point (FPU) QuadSPI controller QorIQ Trust Architecture and ARM TrustZone Two DUARTs Six LPUART interfaces Snoop Control Unit (SCU) Integrated flash controller supporting NAND and 512 KB unified I/D L2 Cache (ECC protection) NOR flash TDM interface Hierarchical interconnect fabric Four GPIO controllers supporting up to 109 general The platform has a single 128-bit AMBA 4 AXI purpose I/O signals Coherency Extensions (ACE) master port, which One 4-channel qDMA controller and one eDMA connects to CCI-400 Interconnect. controller One 8/16/32-bit DDR3L/DDR4 SDRAM memory Global interrupt controller (GIC) controllers Thermal monitor unit (TMU) ECC and interleaving support QUICC Engine ULite block VeTSEC Ethernet complex 32-bit RISC controller for flexible support of the Up to 3x Gigabit Ethernet communications peripherals MII, RMII, RGMII, and SGMII support Serial DMA channel for receive and transmit on all QoS, lossless flow control, and IEEE 1588 serial channels Two universal communication controllers (TDM Up to 4 SerDes lanes for high-speed peripheral and HDLC) supporting 64 multichannels, each interfaces running at 64 Kbps Two PCI Express Gen2 controllers One Serial ATA 3.0 (SATA 1.5, 3.0, 6.0 Gbps) 525 FC-PBGA package, 19 mm x 19 mm controller Two SGMII interfaces supporting 1000 Mbps Integrated audio block Four synchronous audio interfaces (SAI) I2S, AC97, and Codec/DSP interfaces Sony/Philips Digital Interconnect Format (S/PDIF) Asynchronous Sample Rate Converter (ASRC) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 20152016 NXP B.V.Table of Contents 1 Introduction.......................................................................................... 3 3.20 SPI interface.............................................................................. 127 2 Pin assignments.................................................................................... 4 3.21 QuadSPI interface......................................................................133 2.1 LS1020A Ball Map and Pin List............................................... 4 3.22 Enhanced secure digital host controller (eSDHC).....................135 3 Electrical characteristics.......................................................................48 3.23 JTAG controller.........................................................................144 3.1 Overall DC electrical characteristics.........................................48 3.24 I2C interface.............................................................................. 147 3.2 Power sequencing......................................................................54 3.25 GPIO interface...........................................................................150 3.3 Power-down requirements.........................................................58 3.26 GIC interface............................................................................. 152 3.4 Power characteristics.................................................................58 3.27 High-speed serial interfaces (HSSI).......................................... 154 3.5 I/O DC power supply recommendation.....................................60 4 Hardware design considerations...........................................................175 3.6 Power-on ramp rate................................................................... 63 4.1 Power supply design..................................................................175 3.7 Input clocks............................................................................... 63 4.2 Decoupling recommendations...................................................180 3.8 RESET initialization..................................................................70 4.3 SerDes block power supply decoupling recommendations.......181 3.9 DDR3L and DDR4 SDRAM controller.................................... 71 4.4 Connection recommendations................................................... 181 3.10 DUART interface...................................................................... 77 4.5 Thermal......................................................................................186 3.11 Ethernet interface, Ethernet management interface, IEEE Std 4.6 Recommended thermal model...................................................186 1588........................................................................................... 79 4.7 Thermal management information............................................ 187 3.12 QUICC engine specifications....................................................96 5 Package information.............................................................................189 3.13 USB 2.0 interface...................................................................... 102 5.1 Mechanical dimensions of the FC-PBGA................................. 189 3.14 USB 3.0 interface...................................................................... 105 6 Security fuse processor.........................................................................191 3.15 Integrated flash controller (IFC)................................................109 7 Ordering information............................................................................191 3.16 LPUART interface.....................................................................118 7.1 Part numbering nomenclature....................................................191 3.17 Flextimer interface.....................................................................120 7.2 Orderable part numbers addressed by this document................192 3.18 SAI/I2S interface.......................................................................122 8 Revision history....................................................................................193 3.19 SPDIF interface......................................................................... 125 QorIQ LS1020A Data Sheet, Rev. 3, 05/2016 2 NXP Semiconductors