LS1043ASN7MNLB NXP

Document Number LS1043A NXP Semiconductors Rev. 4.1, 08/2019 Data Sheet: Technical Data LS1043A QorIQ LS1043A, LS1023A Data Sheet Features Four SerDes lanes for high-speed peripheral interfaces Three PCI Express 2.0 controllers supporting x4 LS1043A contains 32-bit /64-bit Arm Cortex-A53 operation MPCore Processor with the following capabilities: One Serial ATA (SATA 3.0) controller Speed up to 1.6 GHz Up to four SGMII supporting 1000 Mbit/s 32 KB L1 Instruction Cache w/parity Up to two SGMII supporting 2500 Mbit/s 32 KB L1 Data Cache w/ECC Up to one XFI (10 GbE) interface Neon SIMD Co-processor Up to one QSGMII Arm v8 Cryptography Extensions Supports 1000Base-KX 1 MB unified I/D L2 Cache w/ECC Additional peripheral interfaces Hierarchical interconnect fabric One Quad Serial Peripheral Interface (QSPI) Hardware Managed Data coherency controller, one Deserial Serial Peripheral Interface Up to 400 MHz operation (DSPI) controller Integrated Flash Controller (IFC) supporting NAND One 32-bit DDR3L/DDR4 SDRAM memory controller and NOR flash with 28-bit addressing and 16-bit ECC and interleaving support data Up to 1.6 GT/s Three USB 3.0 controllers with integrated PHY Data Path Acceleration Architecture (DPAA) Enhanced Secure Digital Host Controller (eSDHC) incorporating acceleration for the following functions: supporting SD 3.0, eMMC 4.4, and eMMC 4.5 Packet parsing, classification, and distribution modes (FMan) uQE supporting TDM/HDLC Queue management for scheduling, packet Four I2C controllers sequencing, and congestion management (QMan) Two 16550 compliant DUARTs and six low-power Hardware buffer management for buffer allocation UARTs (LPUARTs) and de-allocation (BMan) General Purpose IO (GPIO), eight Flextimers, five Cryptography acceleration (SEC) Watchdog timer, four independent PWM/counters/ timer Parallel Ethernet interfaces Trust Architecture Up to two RGMII interfaces Debug supporting run control, data acquisition, IEEE 1588 support high-speed trace, and performance/event monitoring NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Introduction.......................................................................................... 3 3.17 Flextimer interface.....................................................................181 2 Pin assignments.................................................................................... 4 3.18 SPI interface.............................................................................. 184 2.1 621 ball layout diagrams........................................................... 4 3.19 QuadSPI interface......................................................................187 2.2 Pinout list (21x21)..................................................................... 10 3.20 Enhanced secure digital host controller (eSDHC).....................189 2.3 780 ball layout diagrams........................................................... 48 3.21 JTAG controller.........................................................................198 2.4 Pinout list...................................................................................54 3.22 I2C interface.............................................................................. 201 3 Electrical characteristics.......................................................................96 3.23 GPIO interface...........................................................................204 3.1 Overall DC electrical characteristics.........................................96 3.24 GIC interface............................................................................. 208 3.2 Power sequencing......................................................................104 3.25 High-speed serial interfaces (HSSI).......................................... 210 3.3 Power down requirements......................................................... 106 4 Hardware design considerations...........................................................232 3.4 Power characteristics.................................................................107 4.1 System clocking........................................................................ 232 3.5 Low power mode saving estimation..........................................110 4.2 Connection recommendations................................................... 242 3.6 I/O power dissipation................................................................ 111 5 Thermal................................................................................................ 247 3.7 Power-on ramp rate................................................................... 113 5.1 Recommended thermal model...................................................249 3.8 Input clocks............................................................................... 114 5.2 Temperature diode.....................................................................249 3.9 RESET initialization..................................................................121 5.3 Thermal management information............................................ 249 3.10 DDR4 and DDR3L SDRAM controller.................................... 121 6 Package information.............................................................................252 3.11 Ethernet interface, Ethernet management interface, IEEE Std 6.1 Package parameters for the FC-PBGA......................................252 1588........................................................................................... 128 6.2 Mechanical dimensions of the FC-PBGA................................. 252 3.12 QUICC engine specifications....................................................152 7 Security fuse processor.........................................................................255 3.13 USB 3.0 interface...................................................................... 157 8 Ordering information............................................................................255 3.14 Integrated Flash Controller........................................................161 8.1 Part numbering nomenclature....................................................255 3.15 LPUART interface.....................................................................178 8.2 Part marking ............................................................................. 256 3.16 DUART interface...................................................................... 180 9 Revision history....................................................................................257 QorIQ LS1043A, LS1023A Data Sheet, Rev. 4.1, 08/2019 2 NXP Semiconductors