MC33816AE NXP

NXP Semiconductors Document Number: MC33816 Rev. 9.0, 1/2019 Data Sheet: Technical data SD6 programmable solenoid 33816 controller for precision solenoid control applications The 33816 is a SMARTMOS programmable gate driver IC for precision solenoid SOLENOID CONTROLLER control applications. The IC consists of five external MOSFET high-side pre- drivers and seven external MOSFET low-side pre-drivers. The 33816 provides a flexible solution for MOSFETs gate drive with a versatile control and optimized latency time. Gate drive, diagnosis, and protection are managed through four independent microcores, and two Code RAM and two Data RAM banks. The IC contains two internal voltage regulators with overvoltage and undervoltage monitoring and protection. There are four current sense modules and VDS monitoring for fault detection and annunciation via a serial peripheral AE SUFFIX (PB-FREE) interface (SPI). 98ASA00237D The device includes both individual charge pump outputs for each high-side pre- 64-PIN LQFP drivers and a high-voltage DC-DC converter low-side pre-driver. EXPOSED PAD These features along with cost effective packaging, make the 33816 ideal for Applications powertrain engine control applications. Automotive (12 V), truck and industrial (24 V) Features powertrain Battery voltage range, 5.0 V < V < 32 V BATT Diesel and gasoline direct injection Pre-drive operating voltage up to 72 V Transmission High-side/ low-side pre-drive PWM capability up to 100 kHz30 nC All pre-drivers have four selectable slew rates Eight selectable, pre-defined VDS monitoring thresholds Encryption for microcode protection Integrated 1.0 MHz back-up clock 33816 V BAT V /V BAT BOOST VBATT B HS1 5.0 V VCC5 G HS1 VCCIO S HS1 VCC2P5 B HS5 G HS5 VCCP Load S HS5 MCU MOSI MOSI D LS1 G LS1 SCLK SCLK CSB CSB D LS6 G LS6 MISO MISO ETPU START1 VSENSEP1 ETPU START6 VSENSEN1 FLAG0 GPIO VSENSEP3 V GPIO FLAG2 VSENSEN3 BOOST GPIO CLK V BAT GPIO DRVEN VBOOST GPIO RESETB G LS7 IRQB GPIO OA 1 ADC VSENSEP4 VSENSEN4 ADC OA 2 Figure 1. MC33816 simplified application diagram NXP B.V. 2019Table of Contents 1 Orderable parts 4 1.1 Cipher Key . 4 2 Internal block diagram . 5 2.1 Simplified internal diagram . 5 3 Pin connections 6 3.1 Pinout diagram 6 3.2 Pin definitions . 6 4 General product characteristics 9 4.1 Maximum ratings 9 4.2 Thermal characteristics 11 4.3 Operating conditions 12 4.4 Supply currents 13 5 General description 14 5.1 Introduction . 14 5.2 Features 14 5.3 Block diagram . 15 5.4 Functional description . 15 6 Functional block description . 16 6.1 Power up/down sequence 16 6.2 Power supplies and monitoring 17 6.3 High-side pre-drivers 33 6.4 Low-side pre-drivers (LS1 - LS6) . 41 6.5 VDS and VSRC monitor and load biasing 45 6.6 Current measurement . 52 6.7 Current measurement for DC-DC conversion . 60 6.8 OA x output pin and multiplexer . 63 6.9 PLL and backup clock . 67 6.10 Digital I/Os 69 6.11 SPI interface . 71 6.12 Internal pull-up and pull-down . 75 6.15 Device logic block description . 81 7 CPU features and operation 160 7.1 Introduction 160 7.2 Features . 160 7.3 Symbols and notation . 161 8 CPU features and operation overview . 164 8.1 Introduction 164 8.2 Memory and signals management programming model 164 8.3 Addressing modes . 168 33816 NXP Semiconductors 2