MC33PF8100EPESR2 NXP

PF8100; PF8200 12-channel power management integrated circuit for high performance applications Rev. 10 5 October 2020 Product data sheet 1 Overview The PF8100/PF8200 is a power management integrated circuit (PMIC) designed for high performance i.MX 8 and S32x based applications. It features seven high efficiency buck converters and four linear regulators for powering the processor, memory and miscellaneous peripherals. Built-in one time programmable memory stores key startup configurations, drastically reducing external components typically used to set output voltage and sequence of 2 external regulators. Regulator parameters are adjustable through high-speed I C after start up offering flexibility for different system states. 2 Features Up to seven high efficiency buck converters Four linear regulators with load switch options RTC supply and coin cell charger Watchdog timer/monitor Monitoring circuit to fit ASIL B safety level One time programmable device configuration 2 3.4 MHz I C communication interface 56-pin 8 x 8 QFN packageNXP Semiconductors PF8100; PF8200 12-channel power management integrated circuit for high performance applications 3 Simplified application diagram PF8x00 PF8x00 PF8x00 IMX8QXP VSNVS VDD_SNVS IMX8QM VSNVS VSNVS VDD_SNVS BUCK1 BUCK1 BUCK1 VDD_MAIN VDD_MAIN GPU0 VDD_MEMC BUCK2 VIN: BUCK2 BUCK2 VIN: VIN: 2.7 V to 2.7 V to 2.7 V to 5.5 V BUCK3 VDD_GPU 5.5 V 5.5 V BUCK3 BUCK3 CPU1 GPU1 (A72) VDD_CPU (A35) BUCK4 BUCK4 BUCK4 BUCK5 VDD_DDRIO BUCK5 CPU0 (A53) VDD_MEMC BUCK5 1.8 V I/O BUCK6 BUCK6 VDD_DDRIO0 VDD_DDRIO1 BUCK6 (LV GPIO) 3.3 V I/O BUCK7 BUCK7 1.8 V I/O 3.3 V I/O BUCK7 (HV GPIO) LDO1 VDD_SCU LDO1 VDD_SCU VDD_SIM LDO1 LDO2 SDCARD0 LDO2 SDCARD0 SDCARD1 LDO2 LDO3 2.5 V I/O LDO3 3.3 V I/O 2.5 V I/O LDO3 LDO4 MISC LDO4 MISC MISC LDO4 CONTROL CONTROL CONTROL INTERFACING AND INTERFACING AND SIGNALS 2 SIGNALS 2 SIGNALS I C COMMUNICATIONS I C COMMUNICATIONS 2 2 2 I C I C I C SIMCARD eMMC Supply SIMCARD Ethernet SD Card SD Card eMMC Supply SD Card Ethernet DRAM DRAM DRAM LPDDR LPDDR_0 LPDDR_1 MISCELLANEOUS MISCELLANEOUS Memory Memory Memory PERIPHERALS PERIPHERALS aaa-028047 Figure 1.Simplified application diagram 4 Ordering information Table 1.Device options Type Package Name Description Version PF8100 (automotive) HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package, SOT684-21 wettable flanks; 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body (DD/SC) PF8200 (automotive) HVQFN56 PF8100 (industrial) HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package, SOT684-21 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body Table 2.Ordering information [1] Part number Target market NXP processor System comments Safety grade OTP ID MC33PF8100A0ES Automotive n/a Not programmed QM n/a [2] MC33PF8100CCES Automotive i.MX8QXP LPDDR4 memory QM