POWER CONTROL LOGIC NXP Semiconductors Document Number: MC34VR500 Rev. 8.0, 8/2018 Advance Information Multi-output DC/DC regulator for 34VR500 QorIQ LS1/T1 family of communications processors The 34VR500 is a high performance, highly integrated, multi-output, Power Management SMARTMOS, DC/DC regulator solution, with integrated power MOSFETs ideally suited for the LS1/T1 family of communication processors. Integrating four switching and five linear regulators, the 34VR500 provides power to the complete system, including the processor, DDR memory, and system peripherals. Features: ES SUFFIX (WF-TYPE) Four buck converters: 98ASA00589D SW1: 4.5 A 56 QFN-EP WF8X8 SW2: 2.0 A Applications: SW3: 2.5 A SW4: 1.0 A, (VTT tracking regulator) Internet of things (IoT) gateway Mobile wireless router Five general purpose linear regulators DDR termination reference voltage (DDR3L and DDR4) MFP printer Network attached storage Programmable low-power modes 2 I C control of all the regulators Automatic teller machine Power Control Logic with processor interface and event detection Auto qualified AEC Q100 grade 2 LS102X VR500 VDD SW1 TA BB VDD SW2 VDDC LDO2 OVDD1/2 LDO4 L1VDD 3.3 V BUS IN LDO5 OVDD GVDD SW3 DDR3 SW4 VTT REFOUT LDO1 HDMI LDO3 Ethernet Figure 1. 34VR500 simplified application diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 2018 NXP B.V.Table of Contents 1 Orderable parts 3 2 Internal block diagram . 4 3 Pin connections 5 3.1 Pinout diagram . 5 3.2 Pin definitions 5 4 General product characteristics 8 4.1 Absolute maximum ratings 8 4.2 Thermal characteristics . 8 4.3 Electrical characteristics . 10 5 General description 12 5.1 Features . 12 5.2 Functional block diagram 13 5.3 Functional description . 13 6 Functional block requirements and behaviors 15 6.1 Start-up 15 6.2 16 MHz and 32 kHz clocks . 18 6.3 Bias and references block description 19 6.4 Power generation 22 6.5 Control interface I2C block description 69 7 Typical applications 80 7.1 Introduction . 80 7.2 Bill of materials 81 7.3 34VR500 layout guidelines . 83 7.4 Thermal information 85 8 Packaging 87 8.1 Packaging dimensions 87 9 Revision history . 90 34VR500 2 NXP Semiconductors