Freescale Semiconductor Document Number: MC56F8006 Rev. 4, 06/2011 Technical Data MC56F8006/MC56F8002 48-pin LQFP 32-pin LQFP Case: 932-03 Case: 873A-03 2 2 7 x 7 mm 7 x 7 mm 28-pin SOIC MC56F8006/MC56F8002 Case: 751F-05 32-pin PSDIP 2 7.5 x 18 mm Digital Signal Controller Case: 1376-02 2 9 x 28.5 mm This document applies to parts marked with 2M53M. RAM. Program flash memory can be independently bulk erased or erased in small pages of 512 bytes (256 words). The 56F8006/56F8002 is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a On-chip features include: single chip, the processing power of a DSP and the Up to 32 MIPS at 32 MHz core frequency functionality of a microcontroller with a flexible set of DSP and MCU functionality in a unified, C-efficient peripherals to create a cost-effective solution. Because of its architecture low cost, configuration flexibility, and compact program On-chip memory code, the 56F8006/56F8002 is well-suited for many 56F8006: 16 KB (8K x 16) flash memory applications. It includes many peripherals that are especially 56F8002: 12 KB (6K x 16) flash memory useful for cost-sensitive applications, including: 2 KB (1K x 16) unified data/program RAM Industrial control One 6-channel PWM module Home appliances Two 28-channel, 12-bit analog-to-digital converters Smart sensors (ADCs) Fire and security systems Two programmable gain amplifiers (PGA) with gain up to Switched-mode power supply and power management 32x Power metering Three analog comparators Motor control (ACIM, BLDC, PMSM, SR, and stepper) One programmable interval timer (PIT) Handheld power tools One high-speed serial communication interface (SCI) with Arc detection LIN slave functionality Medical device/equipment One serial peripheral interface (SPI) Instrumentation One 16-bit dual timer (2 x 16 bit timers) Lighting ballast One programmable delay block (PDB) 2 One SMBus compatible inter-integrated circuit (I C) port The 56800E core is based on a dual Harvard-style architecture One real time counter (RTC) consisting of three execution units operating in parallel, allowing Computer operating properly (COP)/watchdog as many as six operations per instruction cycle. The MCU-style Two on-chip relaxation oscillators 1 kHz and 8 MHz programming model and optimized instruction set allow (400 kHz at standby mode) straightforward generation of efficient, compact DSP and control Crystal oscillator code. The instruction set is also highly efficient for C compilers Integrated power-on reset (POR) and low-voltage interrupt to enable rapid development of optimized control applications. (LVI) module The 56F8006/56F8002 supports program execution from internal JTAG/enhanced on-chip emulation (OnCE) for memories. Two data operands can be accessed from the on-chip unobtrusive, real-time debugging data RAM per instruction cycle. The 56F8006/56F8002 also Up to 40 GPIO lines offers up to 40 general-purpose input/output (GPIO) lines, 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin depending on peripheral configuration. LQFP packages The 56F8006/56F8002 digital signal controller includes up to 16 KB of program flash and 2 KB of unified data/program Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 20092011. All rights reserved.Table of Contents 1 MC56F8006/MC56F8002 Family Configuration 3 8.1 General Characteristics 41 2 Block Diagram .4 8.2 Absolute Maximum Ratings . 42 3 Overview 4 8.3 Thermal Characteristics 43 3.1 56F8006/56F8002 Features 4 8.4 Recommended Operating Conditions . 45 3.2 Award-Winning Development Environment .8 8.5 DC Electrical Characteristics 46 3.3 Architecture Block Diagram .9 8.6 Supply Current Characteristics 51 3.4 Product Documentation 11 8.7 Flash Memory Characteristics . 53 4 Signal/Connection Descriptions .11 8.8 External Clock Operation Timing . 53 4.1 Introduction 11 8.9 Phase Locked Loop Timing . 54 4.2 Pin Assignment .13 8.10 Relaxation Oscillator Timing 54 4.3 56F8006/56F8002 Signal Pins .17 8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 56 5 Memory Maps .29 8.12 External Oscillator (XOSC) Characteristics . 56 5.1 Introduction 29 8.13 AC Electrical Characteristics 57 5.2 Program Map 29 8.14 COP Specifications . 65 5.3 Data Map .30 8.15 PGA Specifications . 65 5.4 Interrupt Vector Table and Reset Vector 31 8.16 ADC Specifications . 66 5.5 Peripheral Memory-Mapped Registers .32 8.17 HSCMP Specifications 68 5.6 EOnCE Memory Map 33 8.18 Optimize Power Consumption . 68 6 General System Control Information .34 9 Design Considerations . 70 6.1 Overview 34 9.1 Thermal Design Considerations . 70 6.2 Power Pins 34 9.2 Electrical Design Considerations . 71 6.3 Reset .34 9.3 Ordering Information 72 6.4 On-chip Clock Synthesis 34 10 Package Mechanical Outline Drawings . 73 6.5 Interrupt Controller 37 10.1 28-pin SOIC Package . 73 6.6 System Integration Module (SIM) .37 10.2 32-pin LQFP 76 6.7 PWM, PDB, PGA, and ADC Connections .38 10.3 48-pin LQFP 79 6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip 10.4 32-Pin PSDIP . 81 Emulator (EOnCE) 39 11 Revision History 83 7 Security Features 39 Appendix A 7.1 Operation with Security Enabled 40 Interrupt Vector Table 83 7.2 Flash Access Lock and Unlock Mechanisms 40 Appendix B 7.3 Product Analysis 41 Peripheral Register Memory Map and Reset Value . 86 8 Specifications .41 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 2 Freescale Semiconductor