Cost-effective, high- performance secure solutions MC56F81xxx DSC Family The new MC56F81xxx digital signal controller (DSC) family features up to 100 MIPS performance and many peripheral enhancements. These products provide extremely cost-effective solutions for digital power conversion and motor control applications. OVERVIEW TARGET APPLICATIONS Switched mode power supply This high-efficiency DSC family is based on the high- performance 56800EX DSP core with frequencies of up to Uninterruptable power supply to 100 MHz. The MC56F81xxx family also extends the DSC Power distribution systems products cost efficiency its NXPs first DSC product family Photovoltaic systems to support ECC-based digital signature algorithm and high- speed operational amplifier. Compared with the MC56F82xxx W ireless charging family, the MC56F81xxx family extends the memory size to Advanced lighting 128 KB flash and 20 KB RAM and adds 64 KB boot ROM. In Advanced motor contr ol addition, the MC56F81xxx family made many enhancements to Appliances motor the MC56F82xxx family, including an enhanced DMA function (eDMA), a more flexible event generator (EVTG), faster 12-bit Industrial motor ADC and full PMBus support. MC56F81xxx DIGITAL SIGNAL CONTROLLERS BLOCK DIAGRAM MC56F81xxx DIGITAL SIGNAL CONTROLLERS BLOCK DIAGRAM Core System Memories Flash SRAM 32-b 56800EX DSC Core Up to 128 KB Up to 20 KB 100 MHz Inter-module Crossbar Boot ROM 64 KB Event Generator 4-ch. eDMA Debug Interface (EVTG) JTAG/EOnCE CRC MRP Digital Signature Algorithm Security Subsystem (DSASS) LVI/POR/Brownout Watchdog Analog Interfaces Timers Clocks 2 x 12-b ADC eFlexPWM NanoEdge 2 2 x I C/PMBus PLL Crystal with PGA 8-ch. Placer Quad Timer 1 x 12-b DAC 1 x SPI 2x PITs 8 MHz OSC 200 kHz OSC 4-ch. 4x ACMP 2 x UART Quadrature Decoder with 8-b DAC 2 x Opamp OptionalFEATURE AND BENEFITS These DSCs ar e pin-to-pin compatible Software Development Kit (SDK) and with the MC56F84xxx, MC56F83xxx and Config Tools 100 MHz 32-bit 56800EX DSP cor e MC56F82xxx families for performance Comprehensive software enablement provides math capabilities needed for and peripheral scalability. advanced power conversion and motor package designed to simplify and control applications. Single-cycle math accelerate application development. Config A digital signatur e algorithm security computations, fractional arithmetic subsystem (DSASS) integrates the ECC- tools allow developers to quickly build a support and parallel moves improve based digital signature authentication custom SDK and leverage pins, clocks and performance, driving tighter and faster function with hardware hash logic and a peripheral tools to generate initialization C control loops. true random number generator (TRNG), code for custom board support. providing enhanced security capability Up to 8 channels of high-r esolution PWM FreeMASTER and helping to save BOM cost. with 312 picosecond resolution enables FreeMASTER is a complimentary, user- higher switching frequencies, helping to Inter -module crossbar and EVTG build an friendly, real-time debug monitor and reduce cost and increase efficiency. interconnection network between external data visualization tool for application pins and module I/Os with hardware T wo 12-bit high-speed low-power ADCs development and information logic/trigger operation capability to each with up to achieve extremely flexible system management. Supporting non-intrusive 1.6 MSPS sampling rate improve configuration. variable monitoring on a running system, system accuracy. Advanced cyclic FreeMASTER allows the data from multiple ADC technology provides high-input An enhanced dir ect memory access impedance and guaranteed monotonicity. variables to be viewed in an evolving (eDMA) controller provides more flexible Each ADC has inner PGA with oscilloscope-like display or in a common two-level loop control, further reducing configurable 2 x/4 x gain. core interruption and helping to increase text format. overall performance. T wo high-speed, low-power operational Some tools are under development. amplifiers, each with up to 8 MHz gain Visit nxp.com/MC56F81xxx for the latest DEVELOPMENT TOOLS bandwidth product (GBP) support available tools. multiple working modes, including open MC56F81000-EVK loop, PGA and voltage follower. The PGA The MC56F81000-EVK is an ultra-low-cost mode supports up to 16x gain. development platform for the MC56F81xxx Four analog comparators with integrated family for rapid prototyping and application 8-bit DACs speed system event development. identification and emergency shutdown of CodeWarrior Development Studio IDE the PWM outputs. Complimentary Special Edition Eclipse- 64 KB to 128 KB flash memory pr ovides based CodeWarrior Development Studio for scalability needed for common digital Microcontrollers is a complete integrated power conversion and motor control development environment that provides a applications. highly visual and automated framework to 20 KB SRAM enables mor e code to be accelerate the development of the most executed from SRAM for faster speed. complex embedded applications. 64 KB boot ROM supports code update 2 through I C and UART and provides user- friendly APIs. PACKAGE OPTIONS Memory Features Package and Temperature Sub-Family Part Number CPU (MHz) 818xx MC56F8186* 100 128 20 312 ps 817xx MC56F8176* 100 128 20 312 ps 817xx MC56F8174* 100 64 12 312 ps 816xx MC56F8166* 100 128 20 10 ns 816xx MC56F8164* 100 64 12 10 ns *Some part numbers are under development. Visit nxp.com/MC56F81xxx for the latest available part numbers. www.nxp.com/MC56F81xxx NXP, the NXP logo, CodeWarrior and Processor Expert are trademarks of NXP B.V. All other product or service names are the property of their respective owners. 2020 NXP B.V. Document Number: MC56F81XXXDSCFS REV 0 Flash (KB) SRAM (KB) DSASS PWM ADC OPAMP DAC SPI 64 LQFP 48 LQFP 32 LQFP 32 QFN Ta 105 C Ta 125 C