MC68LC302AF25CT NXP

Freescale Semiconductor, Inc. MC68QH302/D (Motorola Order Number) 11/97 REV 0 MC68QH302 Advance Information MC68QH302 Quad HDLC Integrated Multiprotocol Processor Technical Summary The MC68QH302, quad HDLC integrated multiprotocol processor, is based on the three- SCC MC68302 family of chips with the addition of the QH protocol and two extra serial DMA channels. The QH302 supports a total of four independent communications channels, handling two HDLC or transparent channels on SCC1 see Figure 1 for a block diagram. In non-QH mode, the QH302 can be used in standard 302 applications as well. To locate any published errata or updates for this document, refer to the website at Freescale Semiconductor, Inc. General-Purpose 3 Timers RAM Interrupt DMA 4 Chip Selects + Controllers Channel Parallel I/O ROM 68000 System Bus M68000 Core 20 Address Lines 8/16 Data Lines 1152 Bytes 8 DMA Dual-Ported Channels RAM Peripheral Bus RISC Controller SCC2 SCP SCC1 + + (2 Channels) SCC3 2 SMCs MC68QH302 Figure 1. MC68QH302 Block Diagram The MC68QH302 supports a full ISDN basic rate interface with one serial channel left over to communicate with the DTE as shown in Figure 2. The dual-channel SCC1 is used to support the two B channels. IDL Flash + MC68QH302 X-FRMR or RAM + and GCI 145572 EEPROM Line I/F 2B + D U-INTF SCC1* or SCC3 145574 S/T INTF SCC2 MC145407 RS232-C Note: *SCC1 = Dual channel SCC, each channel used for a B channel Figure 2. MC68QH302 Supporting a Full ISDN Basic Rate Interface MC68QH302 Technical Summary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc...