MPC7447AEC Freescale Semiconductor Rev. 5, 01/2006 Technical Data MPC7447A RISC Microprocessor Hardware Specifications Contents This document is primarily concerned with the PowerPC 1. Overview . 1 MPC7447A however, unless otherwise noted, all 2. Features 3 information here also applies to the MPC7447. The 3. Comparison with the MPC7447, MPC7445, and MPC7441 7 MPC7447A is an implementation of the PowerPC 4. General Parameters . 9 microprocessor family of reduced instruction set computer 5. Electrical and Thermal Characteristics 9 (RISC) microprocessors. This document describes pertinent 6. Pin Assignments 22 electrical and physical characteristics of the MPC7447A. For 7. Pinout Listings . 23 8. Package Description . 27 functional characteristics of the processor, refer to the 9. System Design Information . 34 MPC7450 RISC Microprocessor Family Reference Manual. 10. Document Revision History . 52 11. Ordering Information 52 To locate any published updates for this document, refer to the Freescale website located at Overview Figure 1. MPC7447A Block Diagram MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 2 Freescale Semiconductor Additional Features 128-Bit (4 Instructions) Instruction Unit Instruction MMU Instruction Queue Time Base Counter/Decrementer (12-Word) Clock Multiplier 128-Entry SRs Branch Processing Unit Fetcher JTAG/COP Interface (Shadow) ITLB 32-Kbyte Thermal/Power Management Tags BTIC (128-Entry) CTR I Cache Performance Monitor IBAT Array Dynamic Frequency Switching (DFS) BHT (2048-Entry) LR Dispatch Temperature Diode Unit Data MMU 32-Kbyte Completion Unit Tags 96-Bit (3 Instructions) 128-Entry D Cache SRs Completion Queue (Original) DTLB (16-Entry) VR Issue GPR Issue FPR Issue DBAT Array (4-Entry/2-Issue) (6-Entry/3-Issue) (2-Entry/1-Issue) Reservation Stations (2-Entry) EA Completes up Vector to three Load/Store Unit Touch instructions PA Queue Vector Touch Engine per clock Reservation Reservation Reservation Reservation Reservation Stations (2) Station Stations (2) Station Station + VR File GPR File (EA Calculation) FPR File Finished L1 Castout 16 Rename 16 Rename 16 Rename Stores Buffers Buffers Buffers Reservation Reservation Integer Integer Floating- Reservation Reservation Integer Integer Unit 2 Unit 1 Station Point Unit Station Station Station Unit 2 Unit 2 (3) L1 Push + x + x + + Vector Vector Vector Completed FPSCR FPSCR Vector Permute Integer Integer Stores Load Mi ss FPU 32-Bit 64-Bit 64-Bit 32-Bit 32-Bit Unit Unit 2 Unit 1 128-Bit 128-Bit Memory Subsystem L1 Store Queue 512-Kbyte Unified L2 Cache Controller System Bus Interface (LSQ) L1 Service Line Load Block 0 (32-Byte) Block 1 (32-Byte) Queues Bus Store Queue Queue (11) Tags Status Status L1 Load Queue (LLQ) Castout Queue (5) / L1 Load Miss (5) Push L2 Store Queue (L2SQ) 1 Queue (6) Snoop Push/ L1 Castouts L2 Prefetch (3) Interventions (4) Instruction Fetch (2) Bus Accumulator Cacheable Store Miss (1) 64-Bit 36-Bit Notes: The Castout Queue and Push Que ue share resources such that they have a combined total of 6 entries. Address Bus Data Bus The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.