Document Number: MPC8641D Freescale Semiconductor Rev. 3, 05/2014 Technical Data MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications Contents 1 Overview 1. Overview . 1 2. Electrical Characteristics 6 The MPC8641 processor family integrates either one or two 3. Power Characteristics 14 Power Architecture e600 processor cores with system 4. Input Clocks . 17 5. RESET Initialization . 20 logic required for networking, storage, wireless 6. DDR and DDR2 SDRAM . 21 infrastructure, and general-purpose embedded applications. 7. DUART . 28 The MPC8641 integrates one e600 core while the 8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MPC8641D integrates two cores. MII Management 29 9. Ethernet Management Interface Electrical This section provides a high-level overview of the MPC8641 Characteristics .43 10. Local Bus . 45 and MPC8641D features. When referring to the MPC8641 11. JTAG . 54 throughout the document, the functionality described applies 2 12. I C . 56 to both the MPC8641 and the MPC8641D. Any differences 13. High-Speed Serial Interfaces (HSSI) 59 14. PCI Express 69 specific to the MPC8641D are noted. 15. Serial RapidIO . 77 Figure 1 shows the major functional units within the 16. Package . 88 17. Signal Listings . 91 MPC8641 and MPC8641D. The major difference between 18. Clocking . 104 the MPC8641 and MPC8641D is that there are two cores on 19. Thermal 108 the MPC8641D. 20. System Design Information 116 21. Ordering Information . 126 22. Document Revision History 128 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2008-2014 Freescale Semiconductor, Inc. All rights reserved.Overview e600 Core Block e600 Core Block e600 Core e600 Core 1-Mbyte 1-Mbyte L2 Cache L2 Cache 32-Kbyte 32-Kbyte 32-Kbyte 32-Kbyte L1 Instruction Cache L1 Data Cache L1 Instruction Cache L1 Data Cache MPX Bus MPX Coherency Module (MCM) Platform Bus Platform SDRAM DDR SDRAM Controller SDRAM DDR SDRAM Controller ROM, Local Bus Controller GPIO (LBC) Multiprocessor Programmable Interrupt IRQs Controller (MPIC) Dual Universal Asynchronous Serial Receiver/Transmitter (DUART) 2 2 I C I C Controller Serial RapidIO 2 2 I C I C Controller Interface or Enhanced TSEC PCI Express OCeaN RMII, GMII, Interface Controller Switch MII, RGMII, x1/x2/x4/x8 PCI Exp (4 GB/s) Fabric TBI, RTBI AND 1x/4x SRIO (2.5 GB/s) 10/100/1Gb OR 2-x1/x2/x4/x8 PCI Express (8 GB/S) Enhanced TSEC RMII, GMII, Controller MII, RGMII, PCI Express TBI, RTBI Interface 10/100/1Gb Enhanced TSEC RMII, GMII, Controller MII, RGMII, TBI, RTBI Four-Channel External 10/100/1Gb DMA Controller Control Enhanced TSEC RMII, GMII, Controller MII, RGMII, TBI, RTBI 10/100/1Gb Figure 1. MPC8641 and MPC8641D MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3 2 Freescale Semiconductor