Document Number: MC9328MX21S Freescale Semiconductor Rev. 1.3, 06/2008 Data Sheet: Technical Data MC9328MX21S Package Information (MAPBGA289) MC9328MX21S Ordering Information: See Table 1 on page 3 266 MHz Contents 1 Introduction 1 Introduction .1 Freescales i.MX family of microprocessors has 2 Signal Descriptions .4 demonstrated leadership in the portable handheld 3 Specifications .12 4 Pin Assignment and Package Information .84 market. Building on the success of the MX (Media 5 Document Revision History .87 Extensions) series, the i.MX21S (MC9328MX21S) provides a leap in performance with an ARM926EJ-S microprocessor core that provides accelerated Java support in addition to highly integrated system functions. The i.MX21S device addresses the needs of multiple markets with intelligent integrated peripherals, advanced ARM processor core, and power management capabilities. The i.MX21S features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 266 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption. On-chip modules such as an LCD controller, USB On-The-Go, 1-Wire interface, and synchronous serial interfaces offer designers a rich suite of peripherals that can enhance many products. For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 20052008. All rights reserved.Introduction devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC) and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN, Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers. The device is packaged in a 289-pin MAPBGA. System Control Connectivity CSPI x 2 i.MX21S JTAG/Multi- ICE SSI x 2 System Boot ARM9 Platform 2 I C Clock Management ARM926EJ-S MAX Audio Mux UART 1, 3, & 4 MMU I Cache Standard System I/O 1-Wire D Cache Bus Control Timers x 3 FIRI Internal Control Memory Control USB OTG/ 1 Host PWM WDOG Memory Expansion RTC Human Interface Memory Interface LCD Controller SDRAMC GPIO MMC/SD x 2 WEIM SLCD Controller PCMCIA/CF DMAC Keypad NFC Figure 1. i.MX21S Functional Block Diagram 1.1 Conventions This document uses the following conventions: OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. Active low signals change from logic level one to logic level zero. Active high signals change from logic level zero to logic level one. Negated means that an asserted discrete signal changes logic state. Active low signals change from logic level zero to logic level one. Active high signals change from logic level one to logic level zero. MC9328MX21S Technical Data, Rev. 1.3 2 Freescale Semiconductor