Freescale Semiconductor, Inc. Order this document by MCF5206/D Communication and Advanced Microprocessor and Memory Consumer Technologies Group Technologies Group MCF5206 Product Brief MCF5206 Integrated Microprocessor The MCF5206 integrated microprocessor combines a ColdFire processor core with several peripheral functions such as a DRAM controller, timers, parallel and serial interfaces, and system integration. Designed for embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system costs. To speed program execution, the on-chip instruction cache and SRAM provide one-cycle access to critical code and data. The MCF5206 processor greatly reduces the time required for system design and implementation by packaging common system functions on chip and providing glueless interfaces to 8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices. The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume markets new levels of price and performance. Based on the concept of variable-length RISC technology, ColdFire combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In defining the ColdFire architecture for embedded processing applications, Motorola incorporated RISC architecture for peak performance and a simplified version of the variable-length instruction set found in the M68000 Family for code density. By using a variable-length instruction set architecture, embedded processor designers using ColdFire RISC processors will enjoy significant system-level advantages over conventional fixed-length RISC architectures. The denser binary code for ColdFire processors consumes less valuable memory than any fixed-length instruction set RISC processor available. This improved code density means more efficient system memory use for a given application, and requires slower, less costly memory to help achieve a target performance level. The integrated peripheral functions provide high performance and flexibility. The DRAM controller supports up to 512 Mbytes of DRAM. The MCF5206 processor supports both page-mode and extended-data-out 2 1 DRAMs. The serial interfaces consist of a programmable full duplex DUART and a separate I C -compatible Motorola bus (M-Bus interface). The two 16-bit general-purpose multimode timers provide separate input and output signals. For system protection, the processor includes a programmable 16-bit software watchdog timer and several bus monitors. In addition, common system functions such as chip-selects, interrupt control, bus arbitration, and IEEE 1149.1 Test (JTAG) support are included. A sophisticated debug interface supports both background-debug mode and real-time trace. This interface is common to all ColdFire-based processors and allows common emulator support across the entire ColdFire Family. ColdFire is a trademark of Motorola. 1. 2 I C bus is a proprietary Philips interface bus. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. SEMICONDUCTOR PRODUCT INFORMATION 1996 Motorola, Inc. All Rights Reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. The primary features of the MCF5206 integrated processor include the following: ColdFire Processor Core Variable-length RISC 32-bit internal address bus with up to 256 Mbytes of off-chip linear address space 32-bit data bus 16 user-visible 32-bit wide registers Supervisor / User modes for system protection Vector base register to relocate exception-vector table Optimized for high-level language constructs 17 MIPS at 33Mhz 512-Byte Direct-Mapped Instruction Cache 512-Byte On-Chip SRAM Provides one-cycle access to critical code and data DRAM Controller Supports up to 32 Mbytes of memory using 4M x 1 DRAMs, 128 Mbytes using 16M x 1 DRAMs, 256 Mbytes using 32x1 DRAMS Programmable refresh timer provides CAS-before-RAS refresh Support for 2 separate memory banks Support for page-mode DRAMs and extended-data-out (EDO) DRAMs Allows external bus master access Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART) Full duplex operation Flexible baud-rate generator Modem control signals available (CTS, RTS) Processor-interrupt capability Compatible with MC68681 DUART programming model Dual 16-Bit General-Purpose Multimode Timers 8-bit prescaler Timer input and output pins 30ns resolution with 33MHz system clock Processor-interrupt capability Motorola Bus (M-Bus) Module Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads 2 Compatible with industry-standard I C Bus Master or slave modes support multiple masters Automatic interrupt generation with programmable level System Interface Glueless bus interface to 8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices 8 programmable chip-select signals Programmable wait states and port sizes Allows external bus masters to access chip-selects System protection 16-bit software watchdog timer with prescaler Double bus fault monitor Bus timeout monitor Spurious interrupt monitor Programmable interrupt controller Low interrupt latency 3 external interrupt inputs Programmable interrupt priority and autovector generator IEEE 1149.1 test (JTAG) support 8-Bit General-Purpose I/O Interface System Debug Support Real-time trace Background debug interface Fully Static 5.0-Volt Operation 160 Pin QFP Package 2 MCF5206 PRODUCT INFORMATION MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc...