Freescale Semiconductor Document Number: MCF54418 Rev. 8, 06/2012 Data Sheet: Technical Data MCF5441x MAPBGA256 MAPBGA196 17mm x 17mm 12 mm x 12 mm MCF5441x ColdFire Microprocessor Data Sheet Version 4 ColdFire Core with EMAC and Enhanced Secure Digital host controller for MMU SD, SDHC, SDIO, MMC, and MMCplus Up to 385 Dhrystone 2.1 MIPS 250 MHz cards 8 KB instruction cache and 8 KB data cache Two ISO7816 smart card interfaces 64 KB internal SRAM dual-ported to Two FlexCAN modules 2 processor local bus and other crossbar switch Six I C bus interfaces with DMA support in masters master mode System boot from NOR, NAND, SPI flash, Two synchronous serial interfaces EEPROM, or FRAM Four 32-bit timers with DMA support Crossbar switch technology (XBS) for Four programmable interrupt timers concurrent access to peripherals or RAM 8-channel, 16-bit motor control PWM timer from multiple bus masters Dual 12-bit ADCs with shared input channels 64-channel DMA controller and multiple conversion trigger sources SDRAM controller supporting full-speed Dual 12-bit DACs with DMA support operation from a single x8 DDR2 component 1-wire module with DMA support up to 250 MHz NAND flash controller 32-bit FlexBus external memory interface for Real-time clock with 32-kHz oscillator, 2 KB RAM, ROM, MRAM, and programmable standby SRAM, and battery backup supply logic input USB 2.0 host controller Up to four DMA-supported serial peripheral USB 2.0 host/device/On-the-Go controller interfaces (DSPI) 8-bit single data rate ULPI port usable by the Up to ten UARTs with single-wire mode dedicated USB host module or the USB support host/device/OTG module Up to five external IRQ interrupts and 2 Dual 10/100 Ethernet MACs with hardware external DMA request/acknowledge pairs CRC checking/generation, IEEE 1588-2002 Up to 16 processor local bus Rapid GPIO pins support, and optional Ethernet switch Up to 87 standard GPIO pins CPU direct-attached hardware accelerator for DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms Random number generator This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2011-2012. All rights reserved.Table of Contents 1 MCF5441x family comparison .4 4.15.2 eSDHC electrical DC characteristics 38 1.1 Ordering information 5 4.16 SIM timing specifications . 38 2 Hardware design considerations .5 4.16.1 General timing requirements 39 2.1 Power filtering .5 4.16.2 Reset sequence 39 2.2 Supply voltage sequencing .7 4.16.3 Power-down sequence . 40 2.2.1 Power-up sequence .8 4.17 SSI timing specifications . 41 2.2.2 Power-down sequence 8 4.18 12-bit ADC specifications 43 2.3 Power consumption specifications .8 4.19 12-bit DAC timing specifications . 44 3 Pin assignments and reset states .9 4.20 mcPWM timing specifications . 45 2 3.1 Signal multiplexing .9 4.21 I C timing specifications . 45 3.2 Pinout196 MAPBGA .19 4.22 Ethernet assembly timing specifications . 46 3.3 Pinout256 MAPBGA .20 4.22.1 Receive signal timing specifications . 47 4 Electrical characteristics .21 4.22.2 Transmit signal timing specifications 47 4.1 Absolute maximum ratings 21 4.22.3 Asynchronous input signal timing 4.2 Thermal characteristics .22 specifications 48 4.3 ESD protection .23 4.22.4 MDIO serial management timing 4.4 Static latch-up (LU) 23 specifications 48 4.5 DC electrical specifications 23 4.23 32-bit timer module timing specifications . 49 4.6 Output pad loading and slew rate .25 4.24 DSPI timing specifications 49 4.7 DDR pad drive strengths 26 4.25 SBF timing specifications 52 4.8 Oscillator and PLL electrical characteristics .26 4.26 1-Wire timing specifications . 53 4.9 Reset timing specifications 28 4.27 General purpose I/O timing specifications 53 4.10 FlexBus timing specifications 28 4.28 Rapid general purpose I/O timing specifications . 53 4.11 NAND flash controller (NFC) timing specifications 30 4.29 JTAG and boundary scan timing specifications 54 4.12 DDR SDRAM controller timing specifications 33 4.30 Debug AC timing specifications 56 4.13 USB transceiver timing specifications 35 5 Package information . 57 4.14 ULPI timing specifications .35 6 Product documentation . 57 4.15 eSDHC timing specifications .36 7 Revision history . 58 4.15.1 eSDHC timing specifications .37 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 2 Freescale Semiconductor