Document Number: IMX50CEC Freescale Semiconductor Rev. 7, 10/2013 Data Sheet: Technical Data MCIMX50 Package Information Plastic Package i.MX50 Applications Case 416 MAPBGA 13 x 13 mm, 0.5 mm pitch Case 416 PoPBGA 13 x 13 mm, 0.5 mm pitch Processors for Case 400 MAPBGA 17 x 17 mm, 0.8 mm pitch Consumer Products Ordering Information See Table 1 on page 7 for ordering information. 1. Introduction . 1 1 Introduction 1.1. Product Overview 2 1.2. Features . 3 The i.MX50 applications processors are 1.3. Ordering Information . 7 1.4. Part Number Feature Comparison . 8 multimedia-focused products offering high-performance 1.5. Package Feature Comparison 9 processing optimized for lowest power consumption. 2. Architectural Overview 10 The i.MX50 processors are Freescale Energy Efficiency 2.1. Block Diagram . 10 3. Modules List 11 Solutions products. 3.1. Special Signal Considerations . 17 4. Electrical Characteristics 20 The i.MX50 is optimized for portable multimedia 4.1. Chip-Level Conditions . 21 applications and features Freescales advanced 4.2. Supply Power-Up/Power-Down Requirements and Restrictions . 29 implementation of the ARM Cortex-A8 core, which 4.3. I/O DC Parameters 31 operates at speeds as high as 1 GHz. The i.MX50 4.4. Output Buffer Impedance Characteristics 37 4.5. I/O AC Parameters 41 provides a powerful display architecture, including a 2D 4.6. System Modules Timing 48 Graphics Processing Unit (GPU) and Pixel Processing 4.7. External Interface Module (EIM) 60 Pipeline (ePXP). Additionally, the i.MX50 includes a 4.8. DRAM Timing Parameters 68 4.9. External Peripheral Interfaces . 73 complete integration of the electrophoretic display 5. Package Information and Contact Assignments . 101 function. The i.MX50 supports DDR2, LPDDR2, and 5.1. 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package Information . 101 LPDDR1 DRAM at clock rate up to 266 MHz to enable 5.2. 13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package a range of performance and power trade-offs. Information . 109 5.3. 17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package The flexibility of the i.MX50 architecture allows it to be Information . 116 used in a variety of applications. As the heart of the 5.4. Signal Assignments 124 6. Revision History 134 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 20112013 Freescale Semiconductor, Inc. All rights reserved.Introduction application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, and displays. 1.1 Product Overview The i.MX50 is designed to enable high-tier portable applications by satisfying the performance requirements of advanced operating systems and applications. 1.1.1 Dynamic Performance Scaling Freescales dynamic voltage and frequency scaling (DVFS) allows the device to run at much lower voltage and frequency with ample processing capacity for tasks, such as audio decode, resulting in significant power reduction. 1.1.2 Multimedia Processing Powerhouse The multimedia performance of the i.MX50 processor ARM Cortex-A8 core is boosted by a multi-level cache system, a NEON coprocessor with SIMD media processing architecture and 32-bit single-precision floating point support, and two vector floating point coprocessors. The system is further enhanced by a programmable smart DMA (SDMA) controller. 1.1.3 Powerful Display System The i.MX50 includes support for both standard LCD displays as well as electrophoretic displays (e-paper). The display subsystem consists of the following modules: Electrophoretic Display Controller (EPDC) (i.MX508 only) The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD TM controller. It is specifically designed to drive E-INK EPD panels, supporting a wide variety of TFT architectures. The goal of the EPDC is to provide an efficient SoC integration of this functionality for e-paper applications, allowing a significant bill of materials cost savings over an external solution while reaching much higher levels of performance and lower power. The EPDC module is defined in the context of an optimized hardware/software partitioning and works in conjunction with the ePXP (see Section 1.1.4, Graphics Accelerators). Enhanced LCD Controller Interface (eLCDIF) The eLCDIF is a high-performance LCD controller interface that supports a rich set of modes and allows interoperability with a wide variety of LCD panels, including DOTCK/RGB and smart panels. The module also supports synchronous operation with the ePXP to allow the processed frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF can support up to 32-bit interfaces. 1.1.4 Graphics Accelerators Integrated graphics accelerators offload processing from the ARM processor, enabling high performance graphic applications at minimum power. i.MX50 Applications Processors for Consumer Products, Rev. 7 2 Freescale Semiconductor