Document Number: IMX8QXPAEC NXP Semiconductors Rev. 3, 05/2020 Data Sheet: Technical Data MIMX8QXnAVxFZAC MIMX8DXnAVxFZAC i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Package Information Applications Processors 21 x 21 mm package case outline 17 x 17 mm package case outline Ordering Information See Section 1.1Table 2 on page 5 1 Introduction 1 1 Introduction 1.1 Ordering Information 5 1.2 System Controller Firmware (SCFW) Requirements6 This data sheet contains specifications for the 1.3 Package options . 7 1.4 Related resources 7 i.MX 8QuadXPlus and 8DualXPlus processors, which, 2 Architectural Overview . 8 along with the i.MX 8DualX processor , comprise the 2.1 Block Diagram . 9 3 Modules List 10 i.MX 8X Family (for i.MX 8DualX specifications, see 3.1 Special Signal Considerations 16 i.MX 8DualX Automotive and Infotainment Processors 3.2 Recommended Connections for Unused Interfaces16 IMX8DXAEC ). The i.MX 8X processors consist of 4 Electrical characteristics . 17 4.1 Chip-level conditions . 17 three to five Arm cores (two to four Arm Cortex -A35 4.2 Power supplies requirements and restrictions 27 and one Cortex -M4F). All devices include separate 4.3 PLL electrical characteristics . 30 4.4 On-chip oscillators . 33 GPU and VPU subsystems as well as a failover-ready 4.5 I/O DC Parameters 36 display controller. Advanced multicore audio processing 4.6 I/O AC Parameters 43 is supported by the Arm cores and a high performance 4.7 Output Buffer Impedance Parameters 45 4.8 System Modules Timing 50 Tensilica HiFi 4 DSP for pre- and post-audio 4.9 General-Purpose Media Interface (GPMI) Timing. 54 processing as well as voice recognition. The i.MX 8X 4.10 External Peripheral Interface Parameters . 63 4.11 Analog-to-digital converter (ADC) 111 Family supports up to three displays with multiple 5 Boot mode configuration 114 display output options, including parallel, MIPI-DSI, 5.1 Boot mode configuration pins . 114 and LVDS. Memory interfaces for this device include: 5.2 Boot devices interfaces allocation 114 6 Package information and contact assignments 116 LPDDR4 (no error correcting code ECC ) 6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch . 116 6.2 FCPBGA, 17 x 17 mm, 0.8 mm pitch . 133 DDR3L (optional ECC) 7 Release Notes . 150 2 Quad SPI or 1 Octal SPI (FlexSPI) eMMC 5.1, RAW NAND, and SD 3.0 NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2018-2020 NXP B.V.Introduction A wide range of peripheral I/Os such as CAN, parallel or MIPI CSI camera input, Gigabit Ethernet, USB 2.0 OTG, USB 3.0 (8QuadXPlus/8DualXPlus only), ADC, and PCIe 3.0 provide impressive flexibility. The i.MX 8QuadXPlus/8DualXPlus processors offer numerous advanced features as shown in this table. Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features Function Feature Multicore architecture provides 2 AArch64 for 64-bit support and new architectural features 4 Cortex-A35 and 1 Cortex-M4F AArch32 for full backward compatibility with ARMv7 cores Cortex-A35 cores support ARM virtualization extensions. Cortex-M4F cores for real-time applications Graphics Processing Unit (GPU) 4 Vec4 shaders with 16 execution units optimized for higher performance Supports OpenGL 3.0, 2.1, OpenGL ES 3.1, 3.0, 2.0, and 1.1 OpenCL 1.2 Full Profile and 1.1 OpenVG 1.1 and Vulkan High-performance 2D Blit Engine H.265 decode (4Kp30) Video Processing Unit (VPU) H.264 decode (4Kp30) WMV9/VC-1 imple decode MPEG 1 and 2 decode AVS decode MPEG4.2 ASP, H.263, Sorenson Spark decode Divx 3.11 including GMC decode ON2/Google VP6/VP8 decode RealVideo 8/9/10 decode JPEG and MJPEG decode H.264 encode (1080p30) Tensilica HiFi 4 DSP for pre- and 640 MHz post-processing Fixed-point and vector-floating-point support 32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and 64 KB of TCM) i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 2 NXP Semiconductors