Document Number: MC33781 Freescale Semiconductor Rev. 5.0, 11/2009 Advance Information Quad DSI 2.02 Master with 33781 Differential Drive and Frequency Spreading The 33781 is a master device for four differential DSI 2.02 buses. It contains the logic to interface the buses to a standard serial DIFFERENTIAL DSI 2.02 MASTER peripheral interface (SPI) port and the analog circuitry to drive data and power over the bus, as well as receive data from the remote slave devices. The differential mode of the 33781 generates lower electromagnetic interference (EMI) in situations where data rates and wiring make this a problem. Frequency spreading further reduces interference by spreading the energy across many frequencies, reducing the energy in any single frequency. EK SUFFIX (PB-FREE) 98ASA10556D Features 32-PIN SOICW EP Four independent differential DSI (DBUS) channels Dual SPI interface Enhanced bus fault performance ORDERING INFORMATION Automatic message cyclical redundancy checking (CRC) Temperature Device Package generation and checking for each channel Range (T ) A Enhanced register set with addressable buffer allows queuing of 4 MCZ33781EK/R2 -40C to 90C 32 SOICW EP independent slave commands at one time for each channel 8- to 16-Bit messages with 0- to 8-Bit CRC Independent frequency spreading for each channel Pseudo bus switch feature on channel 0 Pb-free packaging designated by suffix code EK +5.0V +25V 33781 VCC VCC VSUP1 1.0F DBUS SLAVE SCLK SCLK0 DPH CS CS0 DPL DBUS SLAVE MCU1 MOSI MOSI0 D0H MISO MISO0 D0L DBUS SLAVE RST RST D1H CLK CLK D1L DBUS SLAVE GND D2H VDD 0.1F D2L VSS IDDQ DBUS SLAVE SCLK1 SCLK1 D3H MISO1 MISO1 D3L MCU2 CS1 CS1 AGND GND VSS 2.2nF capacitors from DOH, D0L, GND D1H, D1L, D2H, D2L, D3H and D3L to circuit ground are required for proper operation Figure 1. 33781 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2007-2009. All rights reserved.INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VSUP1 VSUP2 VCC Pseudo Bus Switch DPH 2.5 V Regulator VDD DSIF DSIS D0H DBUS Driver/Receiver D0L CLK DSIR Pseudo Bus Switch DPL DSIF DSIS D1H Spreader DBUS Driver/Receiver D1L VSS IDDQ DSIR DSIF AGND DSIS D2H DBUS TESTIN Driver/Receiver D2L DSIR TESTOUT DSIF DSIS D3H SCLK0 DBUS Driver/Receiver MISO0 SPI0, D3L DSIR Registers and MOSI0 State Machine CS0 T LIM RST GND GND SCLK1 GND MISO1 SPI1, Registers and VSS CS1 State Machine Figure 2. 33781 Internal Block Diagram 33781 Analog Integrated Circuit Device Data 2 Freescale Semiconductor Protocol Engine