Document Number: MPC755EC Freescale Semiconductor Rev. 8, 02/2006 Technical Data MPC755 RISC Microprocessor Hardware Specifications Contents This document is primarily concerned with the MPC755 1. Overview . 1 however, unless otherwise noted, all information here also 2. Features 3 applies to the MPC745. The MPC755 and MPC745 are 3. General Parameters . 5 reduced instruction set computing (RISC) microprocessors 4. Electrical and Thermal Characteristics 6 5. Pin Assignments 25 that implement the PowerPC instruction set architecture. 6. Pinout Listings . 27 This document describes pertinent physical characteristics of 7. Package Description . 32 the MPC755. For information on specific MPC755 part 8. System Design Information . 36 9. Document Revision History . 50 numbers covered by this or other specifications, see 10. Ordering Information 53 Section 10, Ordering Information. For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor Family Users Manual. To locate any published errata or updates for this document, refer to the website listed on the back cover of this document. 1 Overview The MPC755 is targeted for low-cost, low-power systems and supports the following power management featuresdoze, nap, sleep, and dynamic power management. The MPC755 consists of a processor core and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support the L2 cache interface. Figure 1 shows a block diagram of the MPC755. Freescale Semiconductor, Inc., 2006. All rights reserved.Overview Figure 1. MPC755 Block Diagram MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 2 Freescale Semiconductor 128-Bit Instruction Unit (4 Instructions) Branch Processing Fetcher Unit Instruction MMU Additional Features CTR BTIC Time Base Counter/Decrementer LR Instruction Queue 64-Entry SRs Clock Multiplier (6-Word) (Shadow) IBAT 32-Kbyte JTAG/COP Interface BHT Tags Array I Cache Thermal/Power Management ITLB Performance Monitor 2 Instructions 64-Bit Dispatch Unit (2 Instructions) Reservation Station Reservation Reservation Reservation Reservation Station GPR File FPR File (2-Entry) Station Station Station Rename Buffers Rename Buffers (6) (6) System Register 32-Bit 64-Bit 64-Bit Load/Store Unit Floating-Point Integer Unit 1 Integer Unit 2 Unit Unit + + (EA Calculation) + + CR Store Queue FPSCRFPSCR 32-Bit 32-Bit PA EA Completion Unit 60x Bus Interface Unit Data MMU 64-Bit Instruction Fetch Queue Reorder Buffer L2 Bus Interface (6-Entry) Unit SRs L1 Castout Queue (Original) DBAT L2 Castout Queue 32-Kbyte Array Tags Data Load Queue L2 Controller D Cache DTLB L2CR L2 Tags 32-Bit Address Bus 32-/64-Bit Data Bus Not in the MPC745 17-Bit L2 Address Bus 64-Bit L2 Data Bus