Document Number: MPC8250EC Freescale Semiconductor Rev. 2, 07/2009 MPC8250 Hardware Specifications Contents This document contains detailed information on power 1. Features 2 considerations, DC/AC electrical characteristics, and AC 2. Electrical and Thermal Characteristics 6 timing specifications for the MPC8250 PowerQUICC II 3. Clock Configuration Modes . 20 communications processor. 4. Pinout 29 5. Package Description . 55 The following topics are addressed: 6. Ordering Information 59 7. Document Revision History . 59 The MPC8250 is available in two packagesthe standard TBGA package (480 pins) and an alternate PBGA package (516 pins)as described in Section 4, Pinout, and Section 5, Package Description. For more information on PBGA packages, contact your Freescale sales office. Note that throughout this document references to the MPC8250 are inclusive of its PBGA version unless otherwise specified. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2003, 2005, 2009. All rights reserved.Features Figure 1 shows the block diagram for the MPC8250. 16 Kbytes I-Cache I-MMU System Interface Unit (SIU) 60x Bus G2 Core 16 Kbytes Bus Interface Unit D-Cache PCI Bus 32 bits, up to 66 MHz 60x-to-PCI D-MMU Bridge or 60x-to-Local Local Bus Bridge 32 bits, up to 66 MHz Communication Processor Module (CPM) Memory Controller Timers Serial 32 Kbytes Interrupt Dual-Port RAM DMAs Controller Clock Counter Parallel I/O 32-bit RISC Microcontroller 4 Virtual System Functions and Program ROM Baud Rate IDMAs Generators 2 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I C Time Slot Assigner Serial Interface Non-Multiplexed 3 MII 4 TDM Ports I/O Ports Figure 1. MPC8250 Block Diagram 1 Features The major features of the MPC8250 are as follows: Footprint-compatible with the MPC8260 Dual-issue integer core A core version of the EC603e microprocessor System core microprocessor supporting frequencies of 150200 MHz Separate 16-Kbyte data and instruction caches: Four-way set associative Physically addressed LRU replacement algorithm PowerPC architecture-compliant memory management unit (MMU) Common on-chip processor (COP) test interface High-performance (4.45.1 SPEC95 benchmark at 200 MHz 280 Dhrystones MIPS at 200 MHz) MPC8250 Hardware Specifications, Rev. 2 2 Freescale Semiconductor