Document Number: MPC8306SEC Freescale Semiconductor Rev. 1, 09/2011 Technical Data MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8306S 1. Overview . 2 PowerQUICC II Pro processor features. The MPC8306S is 2. Electrical Characteristics 6 a cost-effective, highly integrated communications 3. Power Characteristics 10 processor that addresses the requirements of several 4. Clock Input Timing 11 5. RESET Initialization . 12 networking applications, including residential gateways, 6. DDR2 SDRAM . 13 modem/routers, industrial control, and test and measurement 7. Local Bus . 18 applications. The MPC8306S extends current PowerQUICC 8. Ethernet and MII Management . 21 9. TDM/SI . 28 offerings, adding higher CPU performance, additional 10. HDLC 29 functionality, and faster interfaces, while addressing the 11. USB 31 requirements related to time-to-market, price, power 12. DUART . 33 2 consumption, and board real estate. This document describes 13. I C . 34 14. Timers 36 the electrical characteristics of MPC8306S. 15. GPIO . 37 To locate published errata or updates for this document, refer 16. IPIC 38 17. SPI . 38 to the MPC8306S product summary page on our website 18. JTAG . 40 listed on the back cover of this document or contact your 19. Package and Pin Listings . 44 local Freescale sales office. 20. Clocking 54 21. Thermal . 61 22. System Design Information . 64 23. Ordering Information 67 24. Document Revision History . 69 2011 Freescale Semiconductor, Inc. All rights reserved. Overview 1 Overview The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a 16-bit DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the devicethe unified communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure. 2 x DUART e300c3 Core with Power I2C Management Timers 16-KB 16-KB GPIO I-Cache D-Cache ULPI SPI Enhanced Local Interrupt RTC USB 2.0 HS FPU Controller Bus Controller Host/Device/OTG DDR2 DMA QUICC Engine Block Engine Controller 16 KB Multi-User RAM Accelerators 48 KB Instruction RAM Baud Rate Generators Serial DMA Single 32-bit RISC CP Time Slot Assigner Serial Interface 3 RMII/MII 2x TDM Ports 2x HDLC Figure 1. MPC8306S Block Diagram Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII Ethernet, HDLC and TDM. MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC5 UCC7