Document Number: MPC8360EEC Freescale Semiconductor Rev. 5, 09/2011 Technical Data MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications Contents This document provides an overview of the MPC8360E/58E 1. Overview 1 PowerQUICC II Pro processor revision 2.x TBGA features, including a 2. Electrical Characteristics 7 block diagram showing the major functional components. This device is 3. Power Characteristics . 12 a cost-effective, highly integrated communications processor that 4. Clock Input Timing . 14 addresses the needs of the networking, wireless infrastructure, and 5. RESET Initialization 16 telecommunications markets. Target applications include next generation 6. DDR and DDR2 SDRAM 18 DSLAMs, network interface cards for 3G base stations (Node Bs), 7. DUART 25 routers, media gateways, and high end IADs. The device extends current 8. UCC Ethernet Controller: Three-Speed Ethernet, PowerQUICC II Pro offerings, adding higher CPU performance, MII Management . 25 additional functionality, faster interfaces, and robust interworking 9. Local Bus . 38 10. JTAG 44 between protocols while addressing the requirements related to 2 11. I C 47 time-to-market, price, power, and package size. This device can be used 12. PCI 49 for the control plane and also has data plane functionality. 13. Timers . 51 For functional characteristics of the processor, refer to the MPC8360E 14. GPIO 52 PowerQUICC II Pro Integrated Communications Processor Reference 15. IPIC . 53 Manual, Rev. 3. 16. SPI 54 17. TDM/SI 56 To locate any updates for this document, refer to the MPC8360E product 18. HDLC, BISYNC, Transparent, and Synchronous summary page on our website listed on the back cover of this document UART 59 or contact your Freescale sales office. 19. USB . 62 20. Package and Pin Listings . 63 21. Clocking . 80 22. Thermal 91 1 Overview 23. System Design Information . 96 This section describes a high-level overview including features and 24. Ordering Information 99 general operation of the MPC8360E/58E PowerQUICC II Pro processor. 25. Document Revision History . 100 A major component of this device is the e300 core, which includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture 603e instruction set. The new QUICC Engine module provides termination, interworking, and switching between a 2011 Freescale Semiconductor, Inc. All rights reserved.wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine modules enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine. This figure shows the MPC8360Eblock diagram. System Interface Unit e300 Core (SIU) Security Engine 32KB 32KB Memory Controllers I-Cache D-Cache GPCM/UPM/SDRAM DDRC1 Classic G2 MMUs 32/64 DDR Interface Unit DDRC2 Power FPU PCI Management PCI Bridge Local JTAG/COP Timers Local Bus Bus Arbitration QUICC Engine Module DUART Multi-User Accelerators RAM Baud Rate Serial DMA Generators & Dual I2C 2 Virtual Dual 32-Bit RISC CP DMAs 4 Channel DMA Parallel I/O Interrupt Controller Protection & Configuration System Reset Time Slot Assigner Clock Synthesizer Serial Interface 8 MII/ 2 GMII/ 2 UTOPIA/POS 8 TDM Ports RMII RGMII/TBI/RTBI (124 MPHY) Figure 1. MPC8360E Block Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 2 Freescale Semiconductor MCC UCC1 UCC2 UCC3 UCC4 UCC5 UCC6 UCC7 UCC8 USB SPI1 SPI2