Document Number: MPC8535EEC
Freescale Semiconductor
Rev. 3, 11/2010
Data Sheet: Technical Data
MPC8535E PowerQUICC III
Integrated Processor
MAPBGA783
29 mm x 29 mm
Hardware Specifications
Support for various Ethernet physical interfaces: GMII,
High-performance, 32-bit e500 core, scaling up to
1.25 GHz, that implements the Power Architecture TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII
technology Support TCP/IP acceleration and QOS features
36-bit physical addressing MAC address recognition and RMON statistics support
Double-precision embedded floating point APU using Support ARP parsing and generating wake-up events
64-bit operands based on the parsing results while in deep sleep mode
Embedded vector and scalar single-precision Support accepting and storing packets while in deep
floating-point APUs using 32- or 64-bit operands sleep mode
Memory management unit (MMU) High-speed interfaces (multiplexed) supporting:
Integrated L1/L2 cache Two PCI Express interfaces
L1 cache32-Kbyte data and 32-Kbyte instruction PCI Express 1.0a compatible
L2 cache512-Kbyte (8-way set associative)
One x4/x2/x1 PCI Express interface
DDR2/DDR3 SDRAM memory controller with full ECC
Two x2/x1 ports
support
One SGMII interface
One 64-bit/32-bit data bus
One Serial ATA (SATA) controller supports SATA I and
Up to 250-MHz clock (500-MHz data rate)
SATA I data rates
Supporting up to 16 Gbytes of main memory
PCI 2.2 compatible PCI controller
Using ECC, detects and corrects all single-bit errors and
Two universal serial bus (USB) dual-role controllers
detects all double-bit errors and all errors within a nibble
comply with USB specification revision 2.0
Invoke a level of system power management by
133-MHz, 32-bit, enhanced local bus (eLBC) with memory
asserting MCKE SDRAM signal on-the-fly to put the
controller
memory into a low-power sleep mode
Enhanced secured digital host controller (eSDHC) used for
Both hardware and software options to support
SD/MMC card interface
battery-backed main memory
Support boot capability from eSDHC
Integrated security engine (SEC) optimized to process all
Integrated four-channel DMA controller
2
the algorithms associated with IPsec, IKE, SSL/TLS,
Dual I C and dual universal asynchronous
iSCSI, SRTP, IEEE Std 802.16e, and 3GPP.
receiver/transmitter (DUART) support
XOR engine for parity checking in RAID storage
Programmable interrupt controller (PIC)
applications
Power management, low standby power
Enhanced Serial peripheral interfaces (eSPI)
Support Doze, Nap, Sleep, Jog, and Deep Sleep mode
Support boot capability from eSPI
PMC wake on: LAN activity, USB connection or remote
Two enhanced three-speed Ethernet controllers (eTSECs)
wakeup, GPIO, internal timer, or external interrupt event
with SGMII support
System performance monitor
Three-speed support (10/100/1000 Mbps)
IEEE Std 1149.1-compatible, JTAG boundary scan
Two IEEE Std 802.3, IEEE 802.3u, IEEE 802.3x,
783-pin FC-PBGA package, 29 mm 29 mm
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and
IEEE Std 1588-compatible controllers
2010 Freescale Semiconductor, Inc. All rights reserved.Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3 2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21 3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114
2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31 3.5 SerDes Block Power Supply Decoupling
2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115
2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), 3.7 Pull-Up and Pull-Down Resistor Requirements. . . . . 115
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115
2.10 Ethernet Management Interface Electrical Characteristics 3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116
60 3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117
2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.11 Guidelines for High-Speed Interface Termination . . . 119
2.12 enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74 4.1 Part Numbers Fully Addressed by This Document . . 121
2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2
2.17 I C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.1 Package Parameters for the MPC8535E FC-PBGA . 123
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 5.2 Mechanical Dimensions of the MPC8535E FC-PBGA124
2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90 7 Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . 125
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
2 Freescale Semiconductor