MPC8540EC Freescale Semiconductor Rev. 4.1, 07/2007 Technical Data MPC8540 Integrated Processor Hardware Specifications Contents The MPC8540 integrates a PowerPC processor core built 1. Overview . 2 on Power Architecture technology with system logic 2. Electrical Characteristics 7 required for networking, telecommunications, and wireless 3. Power Characteristics 12 infrastructure applications. The MPC8540 is a member of 4. Clock Timing 14 5. RESET Initialization . 15 the PowerQUICC III family of devices that combine 6. DDR SDRAM 16 system-level support for industry-standard interfaces with 7. DUART . 21 processors that implement the embedded category of the 8. Ethernet: Three-Speed,10/100, MII Management 22 9. Local Bus . 36 Power Architecture technology. For functional 10. JTAG . 46 characteristics of the processor, refer to the MPC8540 11. I2C 48 PowerQUICC III Integrated Host Processor Reference 12. PCI/PCI-X . 50 Manual. 13. RapidIO . 54 14. Package and Pin Listings . 66 To locate any published errata or updates for this document, 15. Clocking 76 contact your Freescale sales office. 16. Thermal . 78 17. System Design Information . 88 18. Document Revision History . 95 19. Device Nomenclature . 100 Freescale Semiconductor, Inc., 2004-2007. All rights reserved.Overview 1 Overview The following section provides a high-level overview of the MPC8540 features. Figure 1 shows the major functional units within the MPC8540. 256KB DDR DDR SDRAM Controller SDRAM L2-Cache/ SRAM e500 Core ROM, SDRAM, Local Bus Controller e500 32 KB L1 32 KB L1 GPIO Coherency I Cache D Cache Module Programmable Core Complex Bus IRQs Interrupt Controller RapidIO-8 RapidIO Controller 16 Gb/s OCeaN PCI-X 64b 10/100 PCI/PCI-X Controller 133 MHz MII ENET 4ch DMA Controller Serial DUART TSEC MII, GMII,TBI, RTBI, RGMII 2 10/100/1G 2 I C I C Controller TSEC MII, GMII,TBI, RTBI, RGMII 10/100/1G Figure 1. MPC8540 Block Diagram 1.1 Key Features The following lists an overview of the MPC8540 feature set. High-performance, 32-bit Book Eenhanced core that implements the Power Architecture 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data Memory management unit (MMU) especially designed for embedded applications Enhanced hardware and software debug support Performance monitor facility (similar to but different from the MPC8540 performance monitor described in Chapter 18, Performance Monitor. MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1 2 Freescale Semiconductor