MPC8541PXALF NXP

MPC8541EEC Freescale Semiconductor Rev. 4.2, 1/2008 Technical Data MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification Contents The MPC8541E integrates a PowerPC processor core 1. Overview 2 built on Power Architecture technology with system logic 2. Electrical Characteristics 7 required for networking, telecommunications, and wireless 3. Power Characteristics . 12 infrastructure applications. The MPC8541E is a member of 4. Clock Timing 14 5. RESET Initialization 15 the PowerQUICC III family of devices that combine 6. DDR SDRAM . 16 system-level support for industry-standard interfaces with 7. DUART 20 processors that implement the embedded category of the 8. Ethernet: Three-Speed, MII Management 21 9. Local Bus . 32 Power Architecture technology. For functional 10. CPM . 42 characteristics of the processor, refer to the MPC8555E 11. JTAG 48 PowerQUICC III Integrated Communications Processor 12. I2C 50 Reference Manual. 13. PCI 52 14. Package and Pin Listings . 54 To locate any published errata or updates for this document 15. Clocking 64 refer to Overview 1Overview The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the major functional units within the MPC8541E DDR DDR SDRAM Controller Security 256 Kbyte SDRAM Engine L2 Cache/ 2 I C Controller SRAM e500 Core e500 DUART 32-Kbyte L1 32-Kbyte L1 Coherency I Cache D Cache Core Complex Module GPIO Bus Local Bus Controller 32b Programmable IRQs Interrupt Controller Serial CPM DMA 64/32b PCI Controller OCeaN FCC ROM FCC 0/32b PCI Controller I-Memory MIIs/RMIIs DMA Controller DPRAM RISC 10/100/1000 MAC Engine SPI MII, GMII, TBI, I/Os I2C Parallel I/O RTBI, RGMIIs 10/100/1000 MAC Baud Rate Generators Timers CPM Interrupt Controller Figure 1. MPC8541E Block Diagram 1.1 Key Features The following lists an overview of the MPC8541E feature set. Embedded e500 Book E-compatible core High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture Dual-issue superscalar, 7-stage pipeline design 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection Lockable L1 cachesentire cache or on a per-line basis Separate locking for instructions and data Single-precision floating-point operations Memory management unit especially designed for embedded applications Enhanced hardware and software debug support Dynamic power management Performance monitor facility MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2 2 Freescale Semiconductor Serial Interfaces