MPC8555EEC
Freescale Semiconductor
Rev. 4.2, 1/2008
Technical Data
MPC8555E PowerQUICC III
Integrated Communications Processor
Hardware Specification
Contents
The MPC8555E integrates a PowerPC processor core
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
built on Power Architecture technology with system logic
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8
required for networking, telecommunications, and wireless
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
infrastructure applications. The MPC8555E is a member of 4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16
the PowerQUICC III family of devices that combine
6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
system-level support for industry-standard interfaces with
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
processors that implement the embedded category of the
8. Ethernet: Three-Speed, MII Management . . . . . . . . . . 22
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Architecture technology. For functional
10. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
characteristics of the processor, refer to the MPC8555E
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PowerQUICC III Integrated Communications Processor
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reference Manual. 13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 56
To locate any published errata or updates for this document
15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
refer to Overview
1Overview
The following section provides a high-level overview of the MPC8555E features. Figure 1 shows the
major functional units within the MPC8555E.
DDR
DDR SDRAM Controller
256-Kbyte
SDRAM Security
Engine
L2 Cache/
2
SRAM
I C Controller
e500 Core
DUART e500
32-Kbyte L1 32-Kbyte L1
Coherency
I Cache D Cache
Core Complex
Module
GPIO
Bus
Local Bus Controller
32b
Programmable
IRQs
Interrupt Controller
Serial
CPM
DMA 64/32b PCI Controller
OCeaN
MPHY
FCC
ROM
UTOPIA
0/32b PCI Controller
FCC
SCC
I-Memory
SCC/USB
MIIs/RMIIs
DMA Controller
SCC
DPRAM
SMC
TDMs
SMC
RISC
10/100/1000 MAC
Engine
SPI
MII, GMII, TBI,
2
I/Os
I C Parallel I/O
RTBI, RGMIIs
10/100/1000 MAC
Baud Rate
Generators
Timers
CPM
Interrupt
Controller
Figure 1. MPC8555E Block Diagram
1.1 Key Features
The following lists an overview of the MPC8555E feature set.
Embedded e500 Book E-compatible core
High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
Dual-issue superscalar, 7-stage pipeline design
32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
Lockable L1 cachesentire cache or on a per-line basis
Separate locking for instructions and data
Single-precision floating-point operations
Memory management unit especially designed for embedded applications
Enhanced hardware and software debug support
Dynamic power management
Performance monitor facility
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
2 Freescale Semiconductor
Serial Interfaces
Time-Slot Assigner