Document Number: MPC8560EC
Freescale Semiconductor
Rev. 5, 05/2010
Technical Data
MPC8560 Integrated Processor
Hardware Specifications
Contents
The MPC8560 integrates a processor core built on Power
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Architecture technology with system logic required for
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
networking, telecommunications, and wireless infrastructure
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
applications. The MPC8560 is a member of the 4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17
PowerQUICC III family of devices that combine
6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
system-level support for industry-standard interfaces with
7. Ethernet: Three-Speed, MII Management . . . . . . . . 22
processors that implement the embedded category of the
8. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power Architecture technology. For functional
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
characteristics of the processor, see the MPC8560
11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PowerQUICC III Integrated Communications Processor
12. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Reference Manual. 13. RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 69
To locate any published errata or updates for this document,
15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
contact your Freescale sales office. 16. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
17. System Design Information . . . . . . . . . . . . . . . . . . . 91
18. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . 98
19. Document Revision History . . . . . . . . . . . . . . . . . . . 99
2010 Freescale Semiconductor, Inc. All rights reserved.Overview
1Overview
The following section provides a high-level overview of the device features. Figure 1 shows the major
functional units within the MPC8560.
256-Kbyte
DDR
DDR SDRAM Controller
L2-Cache/
SDRAM
SRAM
e500 Core
2
I C Controller
e500
32-Kbyte L1 32-Kbyte L1
Coherency
GPIO
I Cache D Cache
Local Bus Controller
Module
32b
Programmable Core Complex Bus
IRQs
Interrupt Controller
Serial RapidIO-8
CPM
RapidIO Controller
DMA
16 Gb/s
MPHY
MCC OCeaN
PCI 64b
ROM
UTOPIAs
MCC PCI Controller
133 MHz
FCC
I-Memory
FCC
MIIs, DMA Controller
FCC
RMIIs
DPRAM
SCC
TDMs
SCC
RISC
10/100/1000 MAC
Engine
SCC
MII, GMII, TBI,
I/Os
SCC Parallel I/O
RTBI, RGMIIs
10/100/1000 MAC
SPI
Baud Rate
Generators
I2C
Timers
CPM
Interrupt
Controller
Figure 1. MPC8560 Block Diagram
1.1 Key Features
The following lists an overview of the MPC8560 feature set:
High-performance, 32-bit Book Eenhanced core that implements the Power Architecture
32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis. Separate locking for instructions and data
Memory management unit (MMU) especially designed for embedded applications
Enhanced hardware and software debug support
Performance monitor facility (similar to but different from the device performance monitor
described in Chapter 18, Performance Monitor.
High-performance RISC CPM operating at up to 333 MHz
CPM software compatibility with previous PowerQUICC families
One instruction per clock
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
2 Freescale Semiconductor
Serial Interfaces
TC - Layer
Time Slot Assigner
Time Slot Assigner