Document Number: MPC862EC Freescale Semiconductor Rev. 3, 2/2006 Technical Data MPC862/857T/857DSL PowerQUICC Family Hardware Specifications Contents This document contains detailed information on power 1. Overview . 2 considerations, DC/AC electrical characteristics, and AC 2. Features 2 timing specifications for the MPC862/857T/857DSL family 3. Maximum Tolerated Ratings . 8 (refer to Table 1 for a list of devices). The MPC862P, which 4. Thermal Characteristics 10 5. Power Dissipation . 10 contains a PowerPC core processor, is the superset device 6. DC Characteristics 11 of the MPC862/857T/857DSL family. For functional 7. Thermal Calculation and Measurement 12 characteristics of the processor, refer to the MPC862 8. Layout Practices 15 9. Bus Signal Timing 15 PowerQUICC Family Users Manual (MPC862UM/D). 10. IEEE 1149.1 Electrical Specifications . 44 11. CPM Electrical Characteristics . 46 12. UTOPIA AC Electrical Specifications . 68 13. FEC Electrical Characteristics . 69 14. Mechanical Data and Ordering Information . 72 15. Document Revision History . 86 Freescale Semiconductor, Inc., 2006. All rights reserved.Overview 1Overview The MPC862/857T/857DSL is a derivative of Freescales MPC860 PowerQUICC family of devices. It is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. Table 1 shows the functionality supported by the members of the MPC862/857T/857DSL family. Table 1. MPC862 Family Functionality Cache Ethernet Part SCC SMC Instruction Data Cache 10T 10/100 Cache MPC862P 16 Kbyte 8 Kbyte Up to 4 1 4 2 MPC862T 4 Kbyte 4 Kbyte Up to 4 1 4 2 MPC857T 4 Kbyte 4 Kbyte 1 1 1 2 1 2 MPC857DSL 4 Kbyte 4 Kbyte 1 1 1 1 1 On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does not support the Time Slot Assigner (TSA). 2 On the MPC857DSL, the SMC (SMC1) is for UART only. 2Features The following list summarizes the key MPC862/857T/857DSL features: Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch, without conditional execution 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1). 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets 4-Kbyte instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets. 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets 4-Kbyte data cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets. Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on-chip-emulation debug mode MPC862/857T/857DSL PowerQUICC Family Hardware Specifications, Rev. 3 2 Freescale Semiconductor