Document Number: MPC885EC Freescale Semiconductor Rev. 7, 07/2010 Technical Data MPC885/MPC880 PowerQUICC Hardware Specifications Contents This hardware specification contains detailed information on 1. Overview . 2 power considerations, DC/AC electrical characteristics, and 2. Features 2 AC timing specifications for the MPC885/MPC880. The 3. Maximum Tolerated Ratings . 9 MPC885 is the superset device of the MPC885/MPC880 4. Thermal Characteristics 10 5. Power Dissipation . 11 family. The CPU on the MPC885/MPC880 is a 32-bit core 6. DC Characteristics 11 built on Power Architecture technology that incorporates 7. Thermal Calculation and Measurement 12 memory management units (MMUs) and instruction and 8. Power Supply and Power Sequencing . 15 9. Layout Practices 16 data caches. For functional characteristics of the 10. Bus Signal Timing 16 MPC885/MPC880, refer to the MPC885 PowerQUICC 11. IEEE 1149.1 Electrical Specifications . 44 Family Reference Manual. 12. CPM Electrical Characteristics . 46 13. UTOPIA AC Electrical Specifications . 69 To locate published errata or updates for this document, refer 14. USB Electrical Characteristics . 71 to the MPC875/MPC870 product summary page on our 15. FEC Electrical Characteristics . 71 website listed on the back cover of this document or, contact 16. Mechanical Data and Ordering Information . 75 17. Document Revision History . 85 your local Freescale sales office. 2010 Freescale Semiconductor, Inc. All rights reserved.Overview 1Overview The MPC885/MPC880 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC885/MPC880 provides enhanced ATM functionality, an additional fast Ethernet controller, a USB, and an encryption block. Table 1 shows the functionality supported by MPC885/MPC880. Table 1. MPC885 Family Cache (Kbytes) Ethernet Security Part SCC SMC USB ATM Support Engine I Cache D Cache 10BaseT 10/100 MPC885 8 8 Up to 3 2 3 2 1 Serial ATM and Yes UTOPIA interface MPC880 8 8 Up to 2 2 2 2 1 Serial ATM and No UTOPIA interface 2Features The MPC885/MPC880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC885/MPC880 features: Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) The 133-MHz core frequency supports 2:1 mode only. The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch and without conditional execution. 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) Instruction cache is two-way, set-associative with 256 sets in 2 blocks Data cache is two-way, set-associative with 256 sets Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on-chip emulation debug mode MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 2 Freescale Semiconductor
