N74F51D,602 NXP

INTEGRATED CIRCUITS 74F51 Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate Product specification 1989 Mar 03 IC15 Data Handbook Philips Semiconductors Product specification Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate 74F51 PIN CONFIGURATION TYPICAL TYPICAL TYPE PROPAGATION SUPPLY CURRENT DELAY (TOTAL) D0a 1 14 V CC 74F51 3.0ns 3.5mA D1a 2 13 D0c D1b 3 12 D0b ORDERING INFORMATION D1c 4 11 D0f COMMERCIAL RANGE D1d 5 10 D0e DESCRIPTION V = 5V 10%, PKG DWG CC T = 0C to +70C Q1 6 9 D0d amb 14-pin plastic DIP N74F51N SOT27-1 GND 7 8 Q0 14-pin plastic SO N74F51D SOT108-1 SF00085 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb, Dnc, Dnd, Dne, Dnf Data inputs 1.0/1.0 20A/0.6mA Q0, Q1 Data outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 9 & 1 1 12 13 9 10 11 2 3 4 5 10 11 8 13 D0a D0b D0c D0d D0e D0f D1a D1b D1c D1d & 12 1 Q0 Q1 2 & 1 3 6 4 86 & 5 V = Pin 14 CC GND = Pin 7 SF00086 SF00087 LOGIC DIAGRAM FUNCTION TABLE FOR 3-INPUT GATES INPUTS OUTPUT 1 D0a D0a D0b D0c D0d D0e D0f Q0 12 D0b H H H X X X L 13 D0c X X X H H H L 8 Q0 All other combinations H 9 D0d NOTES: 10 D0e H = High voltage level 11 D0f L = Low voltage level X = Dont care 2 D1a 3 FUNCTION TABLE FOR 2-INPUT GATES D1b 6 Q1 4 INPUTS OUTPUT D1c 5 D1d D1a D1b D1c D1d Q1 V = Pin 14 H H X X L CC GND = Pin 7 X X H H L SF00088 All other combinations H NOTES: H = High voltage level L = Low voltage level X = Dont care 2 March 3, 1989 8530054 95962