NTA5332 2 NTAG 5 boost - NFC Forum-compliant I C bridge for tiny devices Rev. 3.3 3 July 2020 Product data sheet 544733 COMPANY PUBLIC 1 General description NTAG 5 boost uses active load modulation (ALM) to deliver robust and reliable communication with NFC phones, bringing a new level of convenience to tiny devices. NXPs NTAG 5 boost shrinks the NFC footprint while adding AES security, so designers can deliver ultra-compact devices for use in IoT, consumer, and industrial applications. It offers an NFC Forum-compliant (customer development board is NFC Forum certified - Certification ID: 58625) contactless interface that delivers exceptional read range, giving tiny devices the ability to interact with the cloud and other NFC-enabled devices, including smartphones. V CC ALM 2 l C SRAM 1 0 1 0 1 0 MCU EEPROM e.g 2 TRANSPARENT I C MASTER CHANNEL T SENSOR (energy harvesting) data data event detection (energy) (energy) aaa-034212 Figure 1.NTAG 5 boost overview ALM allows construction of a compact yet highly reliable antenna, creating a significantly smaller footprint without compromising the read range. When operating in ALM mode, the read range is significantly longer than when operating in passive mode. An energy-efficient design, equipped with a hard power-down mode and a standby current of typically less than 10 A, ensures long battery life. 2048 bytes (16384 bits) of user memory can be divided into three areas, and each area can use a different protection level, varying from no protection to 32-/64-bit password protection or up to 128-bit AES-protected read/write access with mutual authentication. Different parties in the value chain can have their own dedicated memory areas for storing access data. The NTAG 5 boost comes with pre-programmed proof-of-origin functionality to verify authenticity. The elliptic curve cryptography (ECC) based originality signature can be locked or reprogrammed by the customer. With NTAG 5 boost, the device can connect to the cloud with a single tap. The connection uses an NFC Forum-compliant data exchange mechanism involving 256 bytes (2048 bits) SRAM to ensure highly interoperable data transfers.NXP Semiconductors NTA5332 2 NTAG 5 boost - NFC Forum-compliant I C bridge for tiny devices 2 Features and benefits Antenna size reduction by a factor of 40, same read range as in passive load modulation Long battery life due to low standby current and hard power-down Adjustable security levels up to mutual AES authentication Flexible split between three open and/or protected memory areas Ensured authenticity of product through value chain Interoperable data exchange according to NFC Forum standards Interoperable and high performance NFC interface ISO/IEC 15693 and NFC Forum Type 5 Tag compliant 64-bit Unique IDentifier Reliable and robust memory 2048 bytes (16384 bits) user EEPROM on top of configuration memory 256 bytes (2048 bits) SRAM for frequently changing data and pass-through mode 40 years data retention Write endurance of 1 000 000 cycles Configurable contact interface 2 I C slave standard (100 kHz) and fast (400 kHz) mode 2 Transparent I C master channel (for example, read sensors without an MCU) One configurable event detection pin 2 Two GPIOs as multiplexed I C lines Two Pulse Width Modulation (PWM) channels as multiplexed GPIOs and/or ED pin 1.62 V to 5.5 V supply voltage Scalable security for access and data protection Disable NFC interface temporarily 2 Disable I C interface temporarily NFC PRIVACY mode Read-only protection as defined in NFC Forum Type 5 Tag Specification Full, read-only, or no memory access based on 32-bit password from both interfaces Optional 64-bit password protection from NFC perspective 128-bit AES authentication as defined in ISO/IEC 15693 ECC-based reprogrammable originality signature Multiple fast data transfer mode Pass-through mode with 256 byte SRAM buffer Standardized data transfer mode (PHDC, TNEP) Low-power budget application support Energy harvesting with configurable output voltage up to 30 mW Low-power standby current typically <10 A Hard power down current typically <0.25 A Very robust architecture -40 C to 105 C for EEPROM read, SRAM and register access -40 C to 85 C for EEPROM write access Extensive product support package Feature specific application notes Development board including software and source code Hands-on training NTA5332 All information provided in this document is subject to legal disclaimers. NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 3 July 2020 COMPANY PUBLIC 544733 2 / 133