NX3P2902BUKZ NXP

NX3P2902B Logic controlled high-side power switch Rev. 2 22 February 2018 Product data sheet 1. General description The NX3P2902B is a high-side load switch which features a low ON resistance P-channel MOSFET. The MOSFET supports more than 500 mA of continuous current and an integrated output discharge resistor to discharge the output capacitance when disabled. Designed for operation from 1.1 V to 3.6 V, it is used in power domain isolation applications to reduce power dissipation and extend battery life. The enable logic includes integrated logic level translation making the device compatible with lower voltage processors and controllers. The NX3P2902B is ideal for portable, battery operated applications due to low ground current and OFF-state current. 2. Features and benefits Wide supply voltage range from 1.1 V to 3.6 V Very low ON resistance: 95 m at a supply voltage of 1.8 V High noise immunity Low OFF-state leakage current (600 nA maximum) 1.2 V control logic at a supply voltage of 3.6 V High current handling capability (500 mA continuous current) Internal output discharge resistor Turn-on slew rate limiting ESD protection: HBM JESD22-A114F Class 3A exceeds 4000 V CDM AEC-Q100-011 revision B exceeds 500 V Specified from 40 C to +85 C 3. Applications Cell phone Digital cameras and audio devices Portable and battery-powered equipmentNX3P2902B NXP Semiconductors Logic controlled high-side power switch 4. Ordering information Table 1. Ordering information Type number Topside Package marking Name Description Version NX3P2902BUK x2 WLCSP4 wafer level chip-scale package 4 bumps 0.77 0.77 0.51 NX3P2902B mm. (Backside coating included) 4.1 Ordering options Table 2. Ordering options Type number Orderable Package Packing method Minimum Temperature part number order quantity NX3P2902BUK NX3P2902BUKZ WLCSP4 Reel 7 Q1/T1 in 3000 T = 40 C to +85 C amb Drypack 5. Functional diagram 9,1 9 5 GFK / 6+,)7(9(/ (1 7 6/( 5 &(: / , 6 2 EN VIN VOUT 001aao342 DDD Fig 1. Logic symbol Fig 2. Logic diagram (simplified schematic) 6. Pinning information 6.1 Pinning 1 3 % LQG H D UHD 9,1 % % *1 (1 DDD DDD Q RS YDUW W7UZVSHLDQH HZSDUWRS QQYL7UVW DH Fig 3. Pin configuration for WLCSP4 Fig 4. Ball mapping for WLCSP4 NX3P2902B All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2 22 February 2018 2 of 15 92 87 PS EX &+ 5*( 1 2172/5 287