LPC3152/3154 ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, NAND flash controller, and audio codec Rev. 1 31 May 2012 Product data sheet 1. General description The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3152/3154 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. The LPC3152/3154 are implemented as a multi-chip module with two side-by-side dies, one for digital functions and one for analog functions, which include Power Supply Unit (PSU), audio codec, RTC, and Li-ion battery charger. 2. Features and benefits 2.1 Key features CPU platform 180 MHz, 32-bit ARM926EJ-S 16 kB D-cache and 16 kB I-cache Memory Management Unit (MMU) Internal memory 192 kB embedded SRAM External memory interface NAND flash controller with 8-bit ECC and AES decryption engine (LPC3154 only) 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM Security AES decryption engine (LPC3154 only) Secure one-time programmable memory for AES key storage and customer use 128 bit unique ID per device for DRM schemes Communication and connectivity High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY 2 Two I S-bus interfaces Integrated master/slave SPI 2 Two master/slave I C-bus interfaces Fast UART Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATALPC3152/3154 NXP Semiconductors ARM926EJ microcontrollers Three-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface Integrated audio codec with stereo ADC and Class AB headphone amplifier System functions Dynamic clock gating and scaling Multiple power domains Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB On the LPC3154 only: secure booting using AES decryption engine from SPI flash, NAND flash, SD/MMC cards, UART, or USB DMA controller Four 32-bit timers Watchdog timer PWM module Master/slave PCM interface Random Number Generator (RNG) General Purpose I/O (GPIO) pins Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access Real-Time Clock (RTC) Power supply Integrated power supply unit Li-ion charger USB charge pump Operating voltage and temperature Core voltage: 1.2 V I/O voltage: 1.8 V, 3.3 V Temperature: 40 C to +85 C 2 TFBGA208 package: 12 12 mm , 0.7 mm pitch 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC3152FET208 TFBGA208 TFBGA208: plastic thin fine-pitch ball grid array package 208 balls SOT930-1 body 12 x 12 x 0.7 mm LPC3154FET208 TFBGA208 TFBGA208: plastic thin fine-pitch ball grid array package 208 balls SOT930-1 body 12 x 12 x 0.7 mm LPC3152 54 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 31 May 2012 2 of 94