UM10430 LPC18xx ARM Cortex-M3 microcontroller Rev. 3.0 26 July 2017 User manual Document information Info Content Keywords LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x, LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20, LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3, SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual Abstract LPC18xx user manual UM10430 NXP Semiconductors LPC18xx User manual Revision history Rev Date Description 3.0 20170726 LPC18xx user manual Modifications: Updated Section 12.2.1.1 Changing the BASE M3 CLK after power-up, reset, or deep power-down mode. Added list item 4. Updated Section 12.2.1.2 Changing the BASE M3 CLK after waking up from deep-sleep or power-down modes. Added list item 3. Updated Table 114 PLL0USB control register (PLL0USB CTRL, address 0x4005 0020) bit description. Added table note to AUTOBLOCK, bit 11. Updated Table 118 PLL0AUDIO control register (PLL0AUDIO CTRL, address 0x4005 0030) bit description. Added table note to AUTOBLOCK, bit 11. Updated Table 123 PLL1 CTRL register (PLL1 CTRL, address 0x4005 0044) bit description. Added table note to AUTOBLOCK, bit 11. 2.9 20170118 LPC18xx user manual Modifications: Fixed formatting issues. Updated Table 19 QSPI devices supported by the boot code and the SPIFI API: Deleted Table: QSPI devices not supported by the boot code. 2.8 20151210 LPC18xx user manual Modifications: Fixed formatting issues. Added CREG1 register. See Table 90 CREG1 register (CREG1, address 0x4004 3008) bit description. Updated text in Section 12.2.1 Configuring the BASE M3 CLK for high operating frequencies: To ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock BASE M4 CLK as described in Section 12.2.1.1. Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in Table 75 Event router inputs USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use for wake-up from sleep and deep-sleep mode USB1: USB1 AHB NEED CLK signal. Not active in power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode. Updated Table 170 LPC1850/30/20/10 Pin description (flashless parts): Fixed PD 3 to beSCT Output 6 was SCT Output 7. UM10430 All information provided in this document is subject to legal disclaimers. NXP B.V. 2017. All rights reserved. User manual Rev. 3.0 26 July 2017 2 of 1284