OM13078 NXP

UM10850 LPC5410x User manual Rev. 2.5 25 April 2017 User manual Document information Info Content Keywords LPC5410x, ARM Cortex-M4, ARM Cortex-M0+, microcontroller, sensor hub Abstract LPC5410x User ManualUM10850 NXP Semiconductors LPC5410x User manual Revision history Rev Date Description 2.5 20170425 Updated Table 253 Register overview: State Configurable Timer SCT/PWM (base address 0x1C01 8000): fixed the base address. Added a Remark to Section 25.7.1.1 Rate calculations and Table 417 Settings for 400 KHz clock rate. Updated Table 456 Transmit data register for SPIn (TXDATCTLSPI 0:1 , address offset 0x2018:0x2118 ) bit description and Table 372 SPI Transmitter Data and Control register (TXDATCTL, offset 0x18) bit description: Changed description of Bit 22 to: Read received data. Received data must be read first and then TxDATA should be written to allow transmission to progress for non DMA cases. In slave mode, an overrun error occurs if received data is not read before new data is received. Added text: On power-up, the BOD is enabled. Power API disables BOD in deep-sleep mode. User must disable BOD reset (bit 2 in the BODCTRL register) and clear bit 6 in the BODCTRL register before calling the power API to enter deep-sleep mode to Section 7.3.4.2 Programming Deep-sleep mode. Updated Table 151 Register overview: I/O configuration (base address 0x4001 C000). Name: PIO0 0:3 and Description: Digital I/O control for port 0 pins PIO0 0 to PIO0 3. Updated Table 278 SCT event control register 0 to 12 (EV 0:12 CTRL, offset 0x304 (EV0 CTRL) to 0x364 (EV12 CTRL)) bit description. Bits 9:6, IOSEL description text: Selects the input or output signal associated with this event (if any). If CKMODE is 1x, the input that is used as the clock may not be selected to trigger events. 2.4 20160913 Updated Table 62 Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit description: Changed the system clock rates of the following: 2 system clocks flash access time (for system clock rates up to 24 MHz). 3 system clocks flash access time (for system clock rates up to 48 MHz). 4 system clocks flash access time (for system clock rates up to 72 MHz). 5 system clocks flash access time (for system clock rates up to 84 MHz). Added 0x5, 6 system clocks flash access time (for system clock rates up to 100 MHz). 2.3 20160906 Added text and a remark to Section 30.1 How to read this chapter. Added a remark to Section 30.3 General description. Added text and a remark to Section 30.4 API description. Added Table 466 Power API calls in LPCOpen power library. Renamed section 30.4.1 to Section 30.4.1 Chip POWER SetPLL. Renamed section 30.4.2 to Section 30.4.2 Chip POWER SetVoltage. Deleted Param0: mode and Low power mode was section 30.4.2.1. Added Section 30.4.3 Chip POWER EnterPowerMode. Updated Section 30.5 Functional description. UM10850 All information provided in this document is subject to legal disclaimers. NXP B.V. 2017. All rights reserved. User manual Rev. 2.5 25 April 2017 2 of 465