LPC802 32-bit ARM Cortex-M0+ microcontroller up to 16 KB flash and 2 KB SRAM 12-bit ADC Comparator Rev. 1.8 25 September 2019 Product data sheet 1. General description The LPC802 is an ARM Cortex-M0+ based, low-cost 32-bit MCU family of processors operating at CPU frequencies of up to 15 MHz. The LPC802 supports 16 KB of flash memory and 2 KB of SRAM. 2 The peripheral complement of the LPC802 includes one I C-bus interface, up to two USARTs, one SPI interface, one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one 12-bit ADC, one analog comparator, function-configurable I/O ports through a switch matrix, and up to 17 general-purpose I/O pins. For additional documentation related to the LPC802 parts, see Section 19 References. 2. Features and benefits System: ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz with single-cycle multiplier and fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. AHB multilayer matrix. Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported. Memory: 16 KB on-chip EEPROM based flash programming memory. Code Read Protection (CRP). 2 KB SRAM. Dual I/O power (LPC802M011JDH20): Independent supplies on each package side permitting level-shifting signals from one off-chip voltage domain to another and/or interfacing directly to off-chip peripherals operating at different supply levels. The switch matrix provides level shifter functionality to allow up to two selected signals to be routed from user-selected pins in one voltage domain to selected pins in the alternate domain. This feature can also be used on a single supply device if voltage level shifting is not required. ROM API support: Boot loader. Supports Flash In-Application Programming (IAP). Supports In-System Programming (ISP) through USART.NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller On-chip ROM APIs for integer divide. Free Running Oscillator (FRO) API. Digital peripherals: High-speed GPIO interface connected to the ARM Cortex-M0+ I/O bus with up to 17 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter. GPIO direction control supports independent set/clear/toggle of individual bits. High-current source output driver (20 mA) on three pins. Switch matrix for flexible configuration of each I/O pin function. CRC engine. Timers: One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, and external count. Two channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates. Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input. Windowed Watchdog timer (WWDT). Analog peripherals: One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports two independent conversion sequences. Comparator with four input pins and external or internal reference voltage. Serial peripherals: Two USART interfaces with pin functions assigned through the switch matrix and one fractional baud rate generators. One SPI controller with pin functions assigned through the switch matrix. 2 One I C-bus interface. Supports Standard mode and Fast mode. Clock generation: Free Running Oscillator (FRO). This oscillator provides selectable 9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range of 0 C to 70 C. 1 MHz low power oscillator can be used as a clock source. Clock output function with divider that can reflect all internal clock sources. Power control: Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and 2 I C peripherals. Wake-up from deep power-down mode on multiple pins. Timer-controlled self wake-up from sleep, deep-sleep, and power-down modes. Power-On Reset (POR). Brownout detect (BOD). LPC802 All information provided in this document is subject to legal disclaimers. NXP Semiconductors B.V. 2019. All rights reserved. Product data sheet Rev. 1.8 25 September 2019 2 of 81